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2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES)最新文献

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Effective Temperature Control Approach for ICs 有效的集成电路温度控制方法
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8443600
A. Samake, Piotr Kocanda, A. Kos
{"title":"Effective Temperature Control Approach for ICs","authors":"A. Samake, Piotr Kocanda, A. Kos","doi":"10.23919/MIXDES.2018.8443600","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8443600","url":null,"abstract":"This paper deals with a technique of dynamic control of power supplying Peltier cooler and fan with respect to generated heat inside chip. RC equivalent model of complex thermal structure is created and implemented in Spice environment. Theoretical investigations of control method and simulation results are presented. The influence of heat sink lateral dimensions and materials on chip temperature value are also evaluated. The proposed approach described in this article enables to keep the chip temperature intervals as low as possible. Hence, this increases the structure reliability and reduces mechanical stress of semiconductor structure. The thermal control technique reduces the cooling energy consumption while reducing risk of condensation. It continuously regulates the power supply of heat pump and active fan based on the information about die power consumption and heat sink temperature. Therefore, the joule heating (heat generated inside Peltier cooler) cannot dominate the cooling capability. Intel's Ivy Bridge processor has been taken into account as a real example used for the investigation.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121255086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
No Static Power Excess Bias Voltage Monitoring Circuit (EBVMC) for SPAD Applications 用于SPAD应用的无静态功率过量偏置电压监测电路(EBVMC)
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436780
N. Lilic, R. Kappel, G. Roehrer, H. Zimmermann
{"title":"No Static Power Excess Bias Voltage Monitoring Circuit (EBVMC) for SPAD Applications","authors":"N. Lilic, R. Kappel, G. Roehrer, H. Zimmermann","doi":"10.23919/MIXDES.2018.8436780","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436780","url":null,"abstract":"A design for monitoring the excess bias voltage of the Single Photon Avalanche Diode (SPAD) is described in this paper. Due to being a mostly digital solution without static power consumption, the presented approach makes it suitable for low power system applications. The core of the new concept uses a latched comparator incorporated with a passive quenching circuit. The algorithm and a system for calibration and monitoring the excess bias voltage are also described. The resolution of controlling the excess bias voltage is equal to a charge pump voltage step. The circuit is designed in 55nm CMOS technology.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115929348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Two Step Power Attack on SHA-3 Based MAC 基于SHA-3 MAC的两步强力攻击
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436910
Chun-Yi Chu, M. Lukowiak
{"title":"Two Step Power Attack on SHA-3 Based MAC","authors":"Chun-Yi Chu, M. Lukowiak","doi":"10.23919/MIXDES.2018.8436910","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436910","url":null,"abstract":"Because of the recent break of the SHA-l hash function, it is expected that in the nearest future there will be an increasing interest in the new SHA-3 algorithm. SHA-3 implements a subset of the Keccak family and has been released as the NIST standard in 2015. SHA-3 based MAC is a keyed-hash message authentication function, which can be used to verify both the data integrity of the message and its source. Previous work demonstrated successful side channel attacks, in particular power attacks on hardware implementations of the SHA-3 based MAC. This work presents a new two step practical attack against SHA-3 based MAC implemented on an FPGA hardware. This new attack can successfully extract the 320-bit secret key with 200,000 traces at 90% success rate.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115950522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Tests for Pilots under Simulated Hypergravity Conditions - Technological Challenges and Tesearch Methodology 模拟超重力条件下飞行员试验。技术挑战和研究方法
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436651
E. Sobotnicka, A. Sobotnicki, Marek Czerw, G. Badura, M. Sobiech, M. Krej, L. Puchalska, L. Dziuda
{"title":"Tests for Pilots under Simulated Hypergravity Conditions - Technological Challenges and Tesearch Methodology","authors":"E. Sobotnicka, A. Sobotnicki, Marek Czerw, G. Badura, M. Sobiech, M. Krej, L. Puchalska, L. Dziuda","doi":"10.23919/MIXDES.2018.8436651","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436651","url":null,"abstract":"The paper presents the application of the orthostatic test and LBNP (lower body negative pressure) test for pilots. The former is used for the assessment of the condition of the cardiovascular system when shifting from a supine position to a head up tilt. The latter consists in applying negative pressure to the lower parts of the body. The paper also describes the existing solutions as regards tilt tables and LBNP chambers with particular emphasis on the original system solution, used in tests for pilots and aviation candidates under simulated hypergravity conditions: ORTO-LBNP. The designed original system is equipped with specially suited measurement modules to record physiological parameters, with a focus on cardiovascular system parameters. Dedicated measurement modules are integrated in one measurement cartridge and allow for simultaneous recording of physiological parameters during the orthostatic and LBNP tests.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123286890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Discrete Implementation of a Semi-Floating Gate Amplifier for Resonating Sensor Front-End 谐振传感器前端半浮门放大器的离散实现
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8443591
L. Marchetti, Y. Berg, M. Azadmehr
{"title":"A Discrete Implementation of a Semi-Floating Gate Amplifier for Resonating Sensor Front-End","authors":"L. Marchetti, Y. Berg, M. Azadmehr","doi":"10.23919/MIXDES.2018.8443591","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8443591","url":null,"abstract":"The growing need of electronic sensors and transducers in modern and portable applications requires to research new design methods, which aim to lower the power consumption and reduce the occupied area of the sensor interface circuitry. In this work we present the implementation of a semi-floating gate amplifier (SFGA) to realize a compact and low power resonating sensor front-end. The prototype has been fabricated by using the commercial integrated circuit CD4007UBE and tested with a power supply of 3.3V. Measurement results show that the main trade-off of this circuit is between gain and bandwidth. The maximum values recorded for these two parameters are: 150VN and 2MHz respectively. The circuit has been tested with an input sinusoidal signal and then connected to a Butterworth Van Dike (BvD) load. This type of load is commonly used to mimic the behavior of a real resonating transducer. The average current absorbed by the amplifier during the normal operation is $6mu A$ leading to a static power consumption of $19.8mu W$. These values refer to a read-out frequency of 100Hz.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127142364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Qucs Frequency Domain Non-Linear Compact Modelling and Simulation of IC Spiral Inductors On Silicon 硅基集成电路螺旋电感的频域非线性紧凑建模与仿真
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8444556
M. Brinson
{"title":"Qucs Frequency Domain Non-Linear Compact Modelling and Simulation of IC Spiral Inductors On Silicon","authors":"M. Brinson","doi":"10.23919/MIXDES.2018.8444556","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8444556","url":null,"abstract":"SPICE AC circuit simulation is fundamentally a small signal network analysis of linear or non-linear circuits operating at specified DC bias conditions, where the circuit component values are assumed not to be functions of AC input signal frequency. In the case of RF circuit simulation this assumption can give rise to significant modelling errors. With the recent improvements in General Public License (GPL) circuit simulators this situation is changing, particularly through the introduction of Frequency Dependent Equation-Defined Device (FEDD) models, non-linear current/voltage static and dynamic Equation-Defined Device (EDD) models and user controlled swept signal frequency simulation employing Harmonic Balance steady state analysis. The main purpose of this paper is to introduce a number of novel modelling and circuit simulation techniques that allow, and enhance, the construction of compact device models with embedded behavioural components whose non-linear properties are functions of AC input signal frequency. To demonstrate these new modelling techniques a compact model for a 10 GHz band width spiral inductor integrated on silicon is introduced, its compact model presented, and finally its simulation performance compared with published measured device data.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131041756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Integration and Testing of Large Scale Diagnostic Systems 大型诊断系统的集成与测试
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436929
P. Plewinski, D. Makowski, P. Perek, A. Napieralski
{"title":"Integration and Testing of Large Scale Diagnostic Systems","authors":"P. Plewinski, D. Makowski, P. Perek, A. Napieralski","doi":"10.23919/MIXDES.2018.8436929","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436929","url":null,"abstract":"The design of the modern Instrumentation and Control (I&C) systems in large-scale projects such as ITER is technically challenging. They often consist of dozens of various complex and distributed systems, which are developed by numerous independent organizations and companies. The integration of the sub-systems into a coherent system is critical for such projects. System testing at all stages of development and integration is a common method of ensuring the proper quality and adherence to the accepted standards. It is necessary that the tests cover all the requirements and functionality of the system and that they can be executed in a repeatable and error-proof way in order to maximize the gains obtained from the use of testing. This paper presents the strategies of testing and system integration illustrated with an example of ITER project. An approach to automated system testing is also proposed.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117008098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of Integrated Circuits and Microsystems 集成电路与微系统设计
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/mixdes.2018.8436586
{"title":"Design of Integrated Circuits and Microsystems","authors":"","doi":"10.23919/mixdes.2018.8436586","DOIUrl":"https://doi.org/10.23919/mixdes.2018.8436586","url":null,"abstract":"","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125552399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Feasibility Studies of EEPROM Memory Implementations in VeSTIC Technology VeSTIC技术中EEPROM存储器实现的可行性研究
2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI: 10.23919/MIXDES.2018.8436679
Bartosz Dec, A. Pfitzner
{"title":"Feasibility Studies of EEPROM Memory Implementations in VeSTIC Technology","authors":"Bartosz Dec, A. Pfitzner","doi":"10.23919/MIXDES.2018.8436679","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436679","url":null,"abstract":"This paper reports a preliminary feasibility study of non-volatile semiconductor memories in VeSTIC technology (Vertical Slit Transistor-based Integrated Circuits). The basic concept of this technology, invented over a decade ago, is a novel 3D architecture, which enables high regularity of the circuit layout and is 3D integration ready. Between evenly distributed vertical pillars, being electrical contacts going all the way through the device layer, all kinds of transistors can be fabricated, and integration of logic components in canvas of density characteristic for memories is accessible. Based on numerical simulations we indicated feasibility of certain EEPROM implementations in VESTICs.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129153318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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