{"title":"Feasibility Studies of EEPROM Memory Implementations in VeSTIC Technology","authors":"Bartosz Dec, A. Pfitzner","doi":"10.23919/MIXDES.2018.8436679","DOIUrl":null,"url":null,"abstract":"This paper reports a preliminary feasibility study of non-volatile semiconductor memories in VeSTIC technology (Vertical Slit Transistor-based Integrated Circuits). The basic concept of this technology, invented over a decade ago, is a novel 3D architecture, which enables high regularity of the circuit layout and is 3D integration ready. Between evenly distributed vertical pillars, being electrical contacts going all the way through the device layer, all kinds of transistors can be fabricated, and integration of logic components in canvas of density characteristic for memories is accessible. Based on numerical simulations we indicated feasibility of certain EEPROM implementations in VESTICs.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/MIXDES.2018.8436679","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper reports a preliminary feasibility study of non-volatile semiconductor memories in VeSTIC technology (Vertical Slit Transistor-based Integrated Circuits). The basic concept of this technology, invented over a decade ago, is a novel 3D architecture, which enables high regularity of the circuit layout and is 3D integration ready. Between evenly distributed vertical pillars, being electrical contacts going all the way through the device layer, all kinds of transistors can be fabricated, and integration of logic components in canvas of density characteristic for memories is accessible. Based on numerical simulations we indicated feasibility of certain EEPROM implementations in VESTICs.