{"title":"No Static Power Excess Bias Voltage Monitoring Circuit (EBVMC) for SPAD Applications","authors":"N. Lilic, R. Kappel, G. Roehrer, H. Zimmermann","doi":"10.23919/MIXDES.2018.8436780","DOIUrl":null,"url":null,"abstract":"A design for monitoring the excess bias voltage of the Single Photon Avalanche Diode (SPAD) is described in this paper. Due to being a mostly digital solution without static power consumption, the presented approach makes it suitable for low power system applications. The core of the new concept uses a latched comparator incorporated with a passive quenching circuit. The algorithm and a system for calibration and monitoring the excess bias voltage are also described. The resolution of controlling the excess bias voltage is equal to a charge pump voltage step. The circuit is designed in 55nm CMOS technology.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.23919/MIXDES.2018.8436780","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A design for monitoring the excess bias voltage of the Single Photon Avalanche Diode (SPAD) is described in this paper. Due to being a mostly digital solution without static power consumption, the presented approach makes it suitable for low power system applications. The core of the new concept uses a latched comparator incorporated with a passive quenching circuit. The algorithm and a system for calibration and monitoring the excess bias voltage are also described. The resolution of controlling the excess bias voltage is equal to a charge pump voltage step. The circuit is designed in 55nm CMOS technology.