Thermal-aware Floorplanning Guidelines for 3D ICs with Integrated Microchannels

Abstract

Future 3D integrated circuits will exhibit very high power densities and therefore novel cooling methods based on integrated microchannels are of considerable interest for chip designers. However, choosing an optimal floorplan for a 3D chip becomes even more difficult when liquid cooling with microchannels is considered. This paper presents thermal simulations results for a sample 3D chip cooled by microchannels and based on the results, provides guidelines for thermal-aware floorplanning. It is shown that two different floorplanning scenarios can be optimal, depending on the chip power profile.