Optimization of the VeSFET Structure Dedicated to Basic Logic Cells in VeSTIC Technology

Abstract

This paper presents a part of feasibility study of VeSTIC (Vertical Slit Transistor-based Integrated Circuit) technology. The goal is an area saving of logic cells designed in this technology by using junction-less VeSFET devices (Vertical-Slit Field-Effect Transistor). Thanks to their feature: two electrically symmetric gates, there is a possibility to greatly reduce the number of elements required to build digital circuits. The use of complementary pair of twin-gate VeSFETs enables to design two-input NOR or NAND cell composed of two instead of four transistors. The combination of the key device parameters: slit width and dopants concentration as well as gate oxide thickness have been established in order to obtain both OR and AND functionality in a single transistor, providing the best distinguishability of the logic states. In particular, we have confirmed that control of the same single bulk channel of VeSFET by two gates ensures to achieve very high drain current ratio (up to le6) corresponding to “11” and “10” input states in the case of the transistor of AND functionality, which is unattainable in other known technologies.