{"title":"Application of Inkjet 3D Printing in MEMS Technique","authors":"R. Walczak","doi":"10.23919/MIXDES.2018.8443601","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8443601","url":null,"abstract":"In this paper, a discussion on applicability of inkjet 3D printing for MEMS fabrication is presented on the base of works carried out by the team leaded by the author. Some remarks on novel technique − 4D printing - are also presented as an emerging technique towards next generation MEMS development.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134278593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modified Neighborhood Determination in Nonlinear State-Space Projective Filtering","authors":"T. Przybyla, T. Pander","doi":"10.23919/MIXDES.2018.8436786","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436786","url":null,"abstract":"Nonlinear state-space projection method (NSSP) is a very useful tool for filtering signals contaminated with broadband noise. The filtering process takes place in a reconstructed embedded space. Time-delay technique is used for reconstructing the embedded space. After that, one signal sample corresponds to a point in a multidimensional space. For each point in the embedded space we seek for its vicinity. This process is time consuming. In this paper we propose an application of clustering method for creation of the signal subspaces. The proposed method is applied to process different types of signals: Lorenz chaotic signal and a real ECG signal. The proposed method appears more effective than NSSP method.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115409823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Otfinowski, A. Krzyzanowska, P. Grybos, R. Szczygiel
{"title":"Multithreshold Pattern Recognition Algorithm for Charge Sharing Compensation in Hybrid Pixel Detectors","authors":"P. Otfinowski, A. Krzyzanowska, P. Grybos, R. Szczygiel","doi":"10.23919/MIXDES.2018.8436791","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436791","url":null,"abstract":"Single photon counting pixel detectors offer an excellent position resolution and allow X-ray photons selection according to their energy. However, for small pixel sizes a charge sharing effect can significantly distort a measured energy spectrum of incoming photons. An on-chip implementation of a sophisticated algorithm using inter-pixel communication is required to overcome this limitation. In this paper we analyze different algorithms implemented in integrated circuits to eliminate the effect of charge sharing and we propose a new architecture to solve this problem. The proposed algorithm is simulated extensively in the wide energy range of X-ray photons (used e.g. in medical imaging), taking into account realistic detector parameters, noise of readout electronics and the problem of mismatch in a pixel matrix.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115944102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Alvis Data Graphs","authors":"M. Szpyrka","doi":"10.23919/MIXDES.2018.8436846","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436846","url":null,"abstract":"Alvis is a formal modelling language intended for describing behaviour of concurrent systems. The formal verification of Alvis models is mainly based on Labelled Transition Systems (LTS graphs) and model checking techniques. The paper deals with the concept of data graphs for Alvis models. Data graphs can be used for verifying Alvis models focused on data flow and manipulation. The graphs are used for reduction of the size of original LTS graphs and for exposing information related to data processing. The presented approach shows that the language can also be used for modelling systems where the data flow rather than the control flow plays the key role.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116206993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Artificial Intelligence Contribution to eHealth Application","authors":"J. Cabestany, D. Martín, Carlos Perez, A. Samà","doi":"10.23919/MIXDES.2018.8436743","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436743","url":null,"abstract":"A presentation of the eHealth related concepts and challenges is done, together with an analysis on how the use of the Artificial Intelligence (AI) techniques can improve the management of the data generated by the eHealth activity, permitting to take more advanced decisions on the treatment and supervision of the patients. A concrete example and developed solution to be applied to the management of Parkinson Disease is presented and discussed.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116288595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Salim El Ghouli, W. Grabinski, J. Sallese, A. Juge, C. Lallement
{"title":"Analog RF and mm-Wave design Tradeoff in UTBB FDSOI: Application to a 35 GHz LNA","authors":"Salim El Ghouli, W. Grabinski, J. Sallese, A. Juge, C. Lallement","doi":"10.23919/MIXDES.2018.8436730","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436730","url":null,"abstract":"The state-of-the art RF and millimeter-wave first-cut circuits design requires simple hand calculation methods to avoid time-consuming iterative simulations. The classical MOSFET sizing methods used in advanced technologies, still rely on questionable and inaccurate concepts. Moreover, the pessimistic rules of thumb proposed for older bulk technologies are no more useful and lead to overdesign. This work takes advantage of the Moderate Inversion and uses low and high frequency figures of merit to provide a convenient sizing method for a 35 GHz Low Noise Amplifier (LNA) in 28 nm UTBB FDSOI technology.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123320267","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High-Speed 32*32 bit Multiplier in 0.18um CMOS Process","authors":"Ebrahim Hosseini, Morteza Mousazadeh, A. Amini","doi":"10.23919/MIXDES.2018.8436851","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436851","url":null,"abstract":"In this paper, a new high-speed and low power unsigned multiplication structure is proposed: based on the proposed algorithm, the input bits of multiplier are broken into several smaller groups of bits and the multiplication of them are calculated concurrently. The final product of multiplication is generated after several rounds of the small group's results aggregation. A 32*32-bit multiplier according to the proposed structure is designed in 0.18um CMOS process. The overall delay of 32*32-bit multiplier is extremely low and is only 2.1ns. The power consumption is 41mW.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117002419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Tomaszewski, K. Domanski, G. Gluszko, A. Sierakowski, D. Szmigiel
{"title":"An Effect of Device Topology in VeSTIC Process on Logic Circuit Operation A Study Based on Ring Oscillator Operation Analysis","authors":"D. Tomaszewski, K. Domanski, G. Gluszko, A. Sierakowski, D. Szmigiel","doi":"10.23919/MIXDES.2018.8436623","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436623","url":null,"abstract":"A design and manufacturing of test structures for characterization of logic integrated circuits in a VeSTIC process developed in ITE, have been described. The logic cell static characteristics as well as waveforms of the 53-stage ring oscillator have been presented. The low oscillation frequency of the circuit has been attributed to the parasitic effects induced by the conservative circuit design based on the VeSTIC process adopted in ITE. Based on the layout and on the process specification, the parasitic elements of the inverter equivalent circuit have been extracted. This equivalent circuit has been used for estimation of the inverter propagation times and their dependence on the supply bias. The same approach has been used for characterization of the CMOS inverter in the ideal VeSTIC process. Frequencies of the two versions of the ring oscillator have been calculated.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127644058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Barkalov, L. Titarenko, M. Mazurkiewicz, Kamil Mielcarek
{"title":"Encoding of Terms in LUT-based Mealy FSMs","authors":"A. Barkalov, L. Titarenko, M. Mazurkiewicz, Kamil Mielcarek","doi":"10.23919/MIXDES.2018.8436684","DOIUrl":"https://doi.org/10.23919/MIXDES.2018.8436684","url":null,"abstract":"A method is proposed for hardware reduction in FPGA-based Mealy FSMs. The method is based on encoding of the terms corresponding to rows of FSM direct structure table. The example of synthesis is given. The application of this method allows reducing the numbers of LUTs in FSM circuits.","PeriodicalId":349007,"journal":{"name":"2018 25th International Conference \"Mixed Design of Integrated Circuits and System\" (MIXDES)","volume":"150B 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132718212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}