An Effect of Device Topology in VeSTIC Process on Logic Circuit Operation A Study Based on Ring Oscillator Operation Analysis

Abstract

A design and manufacturing of test structures for characterization of logic integrated circuits in a VeSTIC process developed in ITE, have been described. The logic cell static characteristics as well as waveforms of the 53-stage ring oscillator have been presented. The low oscillation frequency of the circuit has been attributed to the parasitic effects induced by the conservative circuit design based on the VeSTIC process adopted in ITE. Based on the layout and on the process specification, the parasitic elements of the inverter equivalent circuit have been extracted. This equivalent circuit has been used for estimation of the inverter propagation times and their dependence on the supply bias. The same approach has been used for characterization of the CMOS inverter in the ideal VeSTIC process. Frequencies of the two versions of the ring oscillator have been calculated.