Ultra Low-power, High-speed Digital Comparator

Abstract

This paper is appropriated to a novel 64-bit digital comparator with main targets of low-power consumption and minimum delay from the input to the output. The proposed 64-bit digital comparator has been layout in Cadence and Simulation results using HSPICE software with standard $\pmb{0.18\mu}\mathbf{m}$ CMOS technology parameters, demonstrate 2.8GHz and 335ps delay with the power supply of 1.8volt and also Power-Delay Product (PDP) and power consumption are equal to 0.28pj and $\pmb{862\mu} \mathbf{W}$, respectively.