超低功耗，高速数字比较器

2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES) Pub Date : 2018-06-01 DOI:10.23919/MIXDES.2018.8436901

M. Ghasemzadeh, Saeid Najafibisfar, A. Amini

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引用次数: 2

摘要

本文研究了一种新型的64位数字比较器，其主要目标是低功耗和从输入到输出的最小延迟。采用标准的$\pmb{0.18\mu}\mathbf{m}$ CMOS技术参数，在Cadence上进行了64位数字比较器的布局，并使用HSPICE软件进行了仿真，结果表明，在电源为1.8伏的情况下，该数字比较器具有2.8GHz和335ps的延迟，功率延迟积(PDP)和功耗分别为0.28pj和$\pmb{862\mu} \mathbf{W}$。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Ultra Low-power, High-speed Digital Comparator

This paper is appropriated to a novel 64-bit digital comparator with main targets of low-power consumption and minimum delay from the input to the output. The proposed 64-bit digital comparator has been layout in Cadence and Simulation results using HSPICE software with standard $\pmb{0.18\mu}\mathbf{m}$ CMOS technology parameters, demonstrate 2.8GHz and 335ps delay with the power supply of 1.8volt and also Power-Delay Product (PDP) and power consumption are equal to 0.28pj and $\pmb{862\mu} \mathbf{W}$, respectively.

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2018 25th International Conference "Mixed Design of Integrated Circuits and System" (MIXDES)

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