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2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)最新文献

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Sub-1 V process-compensated MOS current generation without voltage reference sub - 1v工艺补偿MOS电流产生无电压基准
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934221
S. Narendra, D. Klowden, V. De
{"title":"Sub-1 V process-compensated MOS current generation without voltage reference","authors":"S. Narendra, D. Klowden, V. De","doi":"10.1109/VLSIC.2001.934221","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934221","url":null,"abstract":"A sub-1 V process-compensated MOS current generation concept that does not require a reference voltage is presented. A theoretical model for the concept showing reduced sensitivity to variation in process parameters including gate oxide thickness and threshold voltage is derived. MOSFET device measurements and circuit simulation results show reduced process sensitivity and low voltage operation.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123824450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 12-bit mismatch-shaped pipeline A/D converter 一个12位不匹配形状的管道A/D转换器
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934242
A. Shabra, Hae-Seung Lee
{"title":"A 12-bit mismatch-shaped pipeline A/D converter","authors":"A. Shabra, Hae-Seung Lee","doi":"10.1109/VLSIC.2001.934242","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934242","url":null,"abstract":"This paper presents pipeline A/D converters with improved linearity. The linearity improvement is achieved through a combination of oversampling and mismatch shaping, which modulates the distortion energy out-of-band. A 77 dB SFDR is achieved at an oversampling ratio of 4 and a sampling rate of 51 Msample/s, which is a 12 dB improvement compared to a converter with no mismatch shaping. These results were obtained from a test chip fabricated in a 0.35 /spl mu/m CMOS process.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124998827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 1.57 GHz fully integrated very low phase noise quadrature VCO 1.57 GHz全集成极低相位噪声正交压控振荡器
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934210
P. Vancorenland, M. Steyaert
{"title":"A 1.57 GHz fully integrated very low phase noise quadrature VCO","authors":"P. Vancorenland, M. Steyaert","doi":"10.1109/VLSIC.2001.934210","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934210","url":null,"abstract":"A very low phase noise quadrature VCO is presented, featuring an inherently better figure of merit than the existing architectures. Through an improved circuit schematic and a special layout technique, the phase noise of the circuit could be lowered to stand amongst the lowest published. The circuit draws 15 mA from a 2 V supply. The phase noise is -136.5 dBc/Hz@600 kHz and the tuning range is 24% wide at a center frequency of 1.57 GHz. The figure of merit outperforms other published QVCOs.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127116535","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 80
A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs 采用静态锁存器和双极电压可编程防熔丝电路的高密度dram封装后位修复方案
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934197
J. Wee, K. Min, Jong-Tai Park, Sang-Pil Lee, Young-Hee Kim, Tae-Heum Yang, J. Joo, Jin-Yong Chung
{"title":"A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs","authors":"J. Wee, K. Min, Jong-Tai Park, Sang-Pil Lee, Young-Hee Kim, Tae-Heum Yang, J. Joo, Jin-Yong Chung","doi":"10.1109/VLSIC.2001.934197","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934197","url":null,"abstract":"The antifuse programming voltages are changed into bipolar voltages of V/sub CC/ and -V/sub CC/, alleviating high-voltage problems such as permanent device breakdown and achieving a smaller layout area for the antifuse circuit than the previous scheme. In addition, an efficient bit-repair scheme is used instead of the conventional line-repair one, reducing a layout area for the redundancy bits. Using the static latches instead of the dynamic memory cells for the redundancy bits eliminates possible defects in the redundancy area, making this bit-repair scheme robust. The yield improvement using the post-package repair reaches as much as 3% for 0.16 /spl mu/m 256 M SDRAM.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127411466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
1-GHz and 2.8-GHz CMOS injection-locked ring oscillator prescalers 1 ghz和2.8 ghz CMOS注入锁环振荡器预分频器
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934191
Rafael J. Betancourt-Zamora, S. Verma, Thomas H. Lee
{"title":"1-GHz and 2.8-GHz CMOS injection-locked ring oscillator prescalers","authors":"Rafael J. Betancourt-Zamora, S. Verma, Thomas H. Lee","doi":"10.1109/VLSIC.2001.934191","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934191","url":null,"abstract":"We implemented prescalers that can operate up to 2.8-GHz by exploiting the injection locking phenomena in differential CMOS ring oscillators. We tested a 5-stage, 1-GHz injection-locked modulo-8 prescaler fabricated in a 0.24-/spl mu/m CMOS technology that consumes 350 /spl mu/W of power and occupies 0.012 mm/sup 2/ of die area. The locking range is 20 MHz and the locked phase noise is -110 dBc/Hz @ 100 kHz. A 2.8-GHz, 3-stage, modulo-4 divider is also presented.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132372562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 106
A novel sensing scheme for an MRAM with a 5% MR ratio 一种具有5%磁流变比的MRAM传感新方案
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934214
K. Yamada, N. Sakai, Y. Ishizuka, K. Mameno
{"title":"A novel sensing scheme for an MRAM with a 5% MR ratio","authors":"K. Yamada, N. Sakai, Y. Ishizuka, K. Mameno","doi":"10.1109/VLSIC.2001.934214","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934214","url":null,"abstract":"A novel sensing scheme for a magneto-resistive random access memory (MRAM) with a twin cell structure is proposed. It operates by sensing the difference in voltage between a couple of magnetic tunnel junctions (MTJ) in a transitional state. This method can achieve an MRAM with simple circuits, even if the magneto-resistance (MR) ratio is lower than 10%. Moreover, it features good endurance against the dispersion of device characteristics.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124429110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 0 dB-IL, 2140/spl plusmn/30 MHz bandpass filter utilizing Q-enhanced spiral inductors in standard CMOS 一个0 dB-IL, 2140/spl plusmn/ 30mhz带通滤波器，利用标准CMOS中的q增强螺旋电感
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934179
T. Soorapanth, S. Wong
{"title":"A 0 dB-IL, 2140/spl plusmn/30 MHz bandpass filter utilizing Q-enhanced spiral inductors in standard CMOS","authors":"T. Soorapanth, S. Wong","doi":"10.1109/VLSIC.2001.934179","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934179","url":null,"abstract":"A 3/sup rd/-order Chebyshev bandpass filter, that employs on-chip passive elements with Q-enhancement technique, achieves an insertion loss of 0 dB and a passband of 60 MHz around a center frequency of 2140 MHz. Fabricated in a 0.25-/spl mu/m CMOS, the filter operates with 2.5-V supply and 7 mA. The filter occupies an area of 1.3 mm /spl times/2.7 mm.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123014674","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 110
A conditional keeper technique for sub-0.13/spl mu/ wide dynamic gates 低于0.13/spl亩/宽的动态门的条件看守技术
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934184
A. Alvandpour, R. Krishnamurthy, K. Soumyanath, S. Borkar
{"title":"A conditional keeper technique for sub-0.13/spl mu/ wide dynamic gates","authors":"A. Alvandpour, R. Krishnamurthy, K. Soumyanath, S. Borkar","doi":"10.1109/VLSIC.2001.934184","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934184","url":null,"abstract":"Increasing leakage currents seriously limits the robustness of wide dynamic gates. We present an efficient, conditional keeper technique, where a large fraction of the keeper is turned ON only if the dynamic output remains high in the evaluation phase. Thus, strong keepers can be utilized with leaky gates without significant impact on performance of the gates. Compared to the conventional technique, 9-to-35% higher performances have been observed across 8-to-32-bit wide dynamic gates in a 0.13 /spl mu/m technology.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128831395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
A 15-GHz wireless interconnect implemented in a 0.18-/spl mu/m CMOS technology using integrated transmitters, receivers, and antennas 采用集成的发射器、接收器和天线，采用0.18-/spl mu/m CMOS技术实现的15 ghz无线互连
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934225
B. Floyd, C. Hung, K. O. Kenneth
{"title":"A 15-GHz wireless interconnect implemented in a 0.18-/spl mu/m CMOS technology using integrated transmitters, receivers, and antennas","authors":"B. Floyd, C. Hung, K. O. Kenneth","doi":"10.1109/VLSIC.2001.934225","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934225","url":null,"abstract":"Using a 6-metal, copper 0.18-/spl mu/m CMOS technology, a 15-GHz on-chip wireless interconnect system has been demonstrated. The transmission frequency and distance (5.6 mm) of on-chip wireless interconnection have been almost doubled compared to the previously reported system. In addition, an integrated transmitter for on-chip wireless interconnection has been demonstrated. Lastly, the RF potential of CMOS technology for >10 GHz is assessed.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121145456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
A 0.5 V power-supply scheme for low power LSIs using multi-Vt SOI CMOS technology 采用多电压SOI CMOS技术的低功耗lsi 0.5 V供电方案
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934245
T. Fuse, A. Kameyama, M. Ohta, K. Ohuchi
{"title":"A 0.5 V power-supply scheme for low power LSIs using multi-Vt SOI CMOS technology","authors":"T. Fuse, A. Kameyama, M. Ohta, K. Ohuchi","doi":"10.1109/VLSIC.2001.934245","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934245","url":null,"abstract":"Describes a novel power-supply scheme suitable for 0.5V operating LSIs. The system contains the on-chip buck dc-dc converter with over-90% efficiency, 0.5V operating logic, 100MHz operating F/Fs with holding data in the stand-by mode, and the dual-rail level converter. The dc-dc converter TEG, fabricated using 0.35/spl mu/m multi-Vt SOI CMOS process, realized stable recovery characteristics and a final stage efficiency of 92% with 0.5V/10mW output.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115799723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
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