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2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)最新文献

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A JTAG based AC leakage self-test 基于JTAG的交流漏电自检
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934239
T. Rahal-Arabi, G. Taylor
{"title":"A JTAG based AC leakage self-test","authors":"T. Rahal-Arabi, G. Taylor","doi":"10.1109/VLSIC.2001.934239","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934239","url":null,"abstract":"For the last decade, the manufacturing cost per transistor has been exponentially decreasing. The test cost, however, has been decreasing at a much slower rate and now occupies a significant portion of the total cost of a microprocessor. To address this problem, many companies have planned to gradually move away from functional testing to less expensive structural and system level testing. The fundamental cost difference between these techniques comes from a reduction in the number of pins directly driven by the tester. This work describes a new technique that allows a tester to determine if all of the pins on a chip have acceptable leakage without requiring the tester to actually contact each individual pin.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"206 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130465939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Single-chip IF transceiver IC with wide dynamic range variable gain amplifiers for wideband CDMA applications 具有宽动态范围可变增益放大器的单片中频收发器IC，适用于宽带CDMA应用
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934178
T. Maruyama, K. Kaneki, K. Takahashi, H. Sato, T. Iga, N. Kato
{"title":"Single-chip IF transceiver IC with wide dynamic range variable gain amplifiers for wideband CDMA applications","authors":"T. Maruyama, K. Kaneki, K. Takahashi, H. Sato, T. Iga, N. Kato","doi":"10.1109/VLSIC.2001.934178","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934178","url":null,"abstract":"A single-chip IF transceiver IC for wideband code division multiple access systems is described. The chip consists of two variable gain amplifiers, a quadrature modulator, a demodulator, and dual phase locked loops. A new VGA for the receiver is proposed to achieve wide dynamic range. The chip draws 48 mA from 3.0 V. Dynamic ranges of the VGAs for transceiver and receiver are 90 dB and 110 dB respectively.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121164900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Effects of power-supply parasitic components on substrate noise generation in large-scale digital circuits 大规模数字电路中电源寄生元件对衬底噪声产生的影响
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934226
M. Nagata, T. Ohmoto, Y. Hlurasaka, T. Morie, A. Iwata
{"title":"Effects of power-supply parasitic components on substrate noise generation in large-scale digital circuits","authors":"M. Nagata, T. Ohmoto, Y. Hlurasaka, T. Morie, A. Iwata","doi":"10.1109/VLSIC.2001.934226","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934226","url":null,"abstract":"Activity controllable noise source and arrayed substrate voltage detectors use a 0.25-/spl mu/m, 2.5-V CMOS technology and enable substrate noise measurements with controlled logic density/activity distributions. These circuits are used for exploring effects of power-supply parasitic components on substrate noise generation in practical large-scale CMOS digital circuits. Spatially distributed parasitic impedances on power-supply and return wirings cause the noise generation locally, and moreover, screen the effect of noise attenuation by parasitic capacitances of logic elements working as charge reservoirs.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122962186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A 0.13 /spl mu/m 6 GHz 256/spl times/32b leakage-tolerant register file 一个0.13 /spl mu/m 6 GHz 256/spl次/32b容漏寄存器文件
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934182
R. Krishnamurthy, A. Alvandpour, G. Balamurugan, N. Shanbhagh, K. Soumyanath, S. Borkar
{"title":"A 0.13 /spl mu/m 6 GHz 256/spl times/32b leakage-tolerant register file","authors":"R. Krishnamurthy, A. Alvandpour, G. Balamurugan, N. Shanbhagh, K. Soumyanath, S. Borkar","doi":"10.1109/VLSIC.2001.934182","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934182","url":null,"abstract":"This paper describes a 256/spl times/32b 4-read, 4-write ported register file for 6 GHz operation in 1.2 V, 0.13 /spl mu/m technology. The local bitline uses a pseudo-static leakage tolerant scheme to achieve 8% faster read performance and 36% higher DC noise robustness (with 6/spl times/ active leakage reduction) compared to dual-Vt scheme optimized for high-performance.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126174224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Fully integrated 2.2 mW CMOS front-end for a 900 MHz zero-IF wireless receiver 完全集成的2.2 mW CMOS前端900 MHz零中频无线接收机
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934255
S. Mahdavi, A. Abidi
{"title":"Fully integrated 2.2 mW CMOS front-end for a 900 MHz zero-IF wireless receiver","authors":"S. Mahdavi, A. Abidi","doi":"10.1109/VLSIC.2001.934255","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934255","url":null,"abstract":"Wireless sensors and wearable wireless devices need low bit-rate receivers which dissipate a total power of less than 5 mW and operate from a single cell. They must also be highly integrated for small physical volume. As is customary, CMOS is the technology of choice. In previous work, we have developed a complete 900 MHz receiver for FLEX paging signals which dissipates 4.5 mW from 1.5V, but needs several high quality off-chip inductors. This work advances the state of the art by integrating these external components in the RF and IF sections of a 900 MHz zero-IF receiver. There are three design challenges: (a) Low current consumption, (b) low voltage operation, and (c) low 1/f noise at zero IF. Integrated in 0.35/spl mu/m CMOS, the receiver front-end including LNA and two mixer stages dissipates only 2.2 mW. As low power design is a universal concern in RF-IC design, the methodology described here is expected to be of value in many other applications.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122012775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An area-efficient 2 GB/s 256 Mb packet-based DRAM with daisy-chained redundancy scheme 一个区域高效的2gb /s 256 Mb基于数据包的DRAM，采用菊花链冗余方案
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934187
B.-S. Moon, J. Chai, J. Kim, S.-M. Yim, S.-A. Kim, C. Kim, S. Cho
{"title":"An area-efficient 2 GB/s 256 Mb packet-based DRAM with daisy-chained redundancy scheme","authors":"B.-S. Moon, J. Chai, J. Kim, S.-M. Yim, S.-A. Kim, C. Kim, S. Cho","doi":"10.1109/VLSIC.2001.934187","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934187","url":null,"abstract":"An area-efficient packet-based 256 Mb DRAM with a 4 bank architecture and a peak bandwidth of 1.0 Gbps/pin at V/sub cc/=2.35 V, Temp=100/spl deg/C is developed. This chip features a daisy chained redundancy scheme, an area-efficient logic block placement and routing technique and a process insensitive DLL with duty error reduction scheme to overcome large chip size penalty and to improve chip yield.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114810615","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 200 MHz 7th-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25 /spl mu/m CMOS process 采用0.25 /spl mu/m CMOS工艺设计的非线性抑制200 MHz 7阶等纹连续滤波器
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934230
T. Morie, H. Fujiyama, S. Dosho
{"title":"A 200 MHz 7th-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25 /spl mu/m CMOS process","authors":"T. Morie, H. Fujiyama, S. Dosho","doi":"10.1109/VLSIC.2001.934230","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934230","url":null,"abstract":"7th order equiripple filter with cutoff frequency of 200 MHz is developed in a 0.25 /spl mu/m CMOS process. A new design method has been adopted to obtain enough accuracy and linearity in high frequency operation. Optimal device sizes are determined that maximize the accuracy. The most suitable filter configuration is determined that suppresses the nonlinearity of the transconductors. Experimental results satisfy group delay variation of /spl plusmn/5% and THD of less than 1% for a 400 mVpp differential input.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"249 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114285477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 800 MHz single cycle access 32 entry fully associative TLB with a 240 ps access match circuit 一个800mhz单周期访问32项全关联TLB与240ps访问匹配电路
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934249
M. Sumita
{"title":"A 800 MHz single cycle access 32 entry fully associative TLB with a 240 ps access match circuit","authors":"M. Sumita","doi":"10.1109/VLSIC.2001.934249","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934249","url":null,"abstract":"A high-speed content addressable memory (CAM) match circuit is the key for a system LSI in this digital network era, such as consumer electronics and digital communication. For example, a microprocessor with a memory management unit (MMU) has usually a translation look-aside buffer (TLB) including the CAM. The CAM is demanded small area, high speed, and also low power. In this paper we propose and study two types of CAM match circuit for a fully associative TLB.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131040041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A reconfigurable multilevel parallel graphics cache memory with 75 GB/s parallel cache replacement bandwidth 具有75 GB/s并行缓存替换带宽的可重构多级并行图形缓存
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934250
Se-Jeong Park, Jeong-Su Kim, Ramchan Woo, Se-Joong Lee, Kangmin Lee, Tae-Hum Yang, Jin-Yong Jung, H. Yoo
{"title":"A reconfigurable multilevel parallel graphics cache memory with 75 GB/s parallel cache replacement bandwidth","authors":"Se-Jeong Park, Jeong-Su Kim, Ramchan Woo, Se-Joong Lee, Kangmin Lee, Tae-Hum Yang, Jin-Yong Jung, H. Yoo","doi":"10.1109/VLSIC.2001.934250","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934250","url":null,"abstract":"A dedicated single-chip multilevel parallel graphics cache memory for high-speed parallel texture mapping in PC graphics has been fabricated by a 0.16 /spl mu/m DRAM technology. The proposed cache architecture is composed of four components: 1) an 8 MB DRAM L2 cache, 2) eight 16 KB SRAM L1 parallel caches, 3) eight pipelined texture data filters, 4) serial-to-parallel latches. The refill bandwidth of the parallel L1 cache is maximized up to 75 GB/sec by a hidden double data transfer scheme between the L2 and L1 caches. Furthermore, by adaptive sub-wordline activation scheme, the line sizes of the L2 and L1 caches are reconfigurable for achieving optimal cache miss rate and lower power consumption. The SRAM L1 caches and the texture filters by use of parallel pipelined structures result in higher system performance.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128140997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Bit line coupling scheme and electrical fuse circuit for reliable operation of high density DRAM 高密度DRAM可靠工作的位线耦合方案和保险丝电路
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934186
K. Lim, S. Kang, J. Choi, Jaehoon Joo, Younsang Lee, Jinseok Lee, Sooin Cho, Byungil Ryu
{"title":"Bit line coupling scheme and electrical fuse circuit for reliable operation of high density DRAM","authors":"K. Lim, S. Kang, J. Choi, Jaehoon Joo, Younsang Lee, Jinseok Lee, Sooin Cho, Byungil Ryu","doi":"10.1109/VLSIC.2001.934186","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934186","url":null,"abstract":"Two design techniques are presented to improve the yield of high density DRAM product. One is bit line coupling (BLC) scheme and the other is electrical fuse (E-Fuse) circuit for reliable field programmable repair scheme. We obtain an improvement of 100 ms for the data retention time (tREF) using the BLC scheme. BLC scheme also improves the low VCC margin by 0.3 V and the RAS to CAS delay time (tRCD) by 1.5 ns. Differential current evaluation for the E-fuse implementation shows polysilicon fuse fail rate <10/sup -12/.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"571 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116281661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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