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2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)最新文献

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A 1.8 V single-inductor dual-output switching converter for power reduction techniques 一种1.8 V单电感双输出开关变换器，用于功率降低技术
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934219
D. Ma, W. Ki, C. Tsui, P. Mok
{"title":"A 1.8 V single-inductor dual-output switching converter for power reduction techniques","authors":"D. Ma, W. Ki, C. Tsui, P. Mok","doi":"10.1109/VLSIC.2001.934219","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934219","url":null,"abstract":"A 1.8 V integrated single-inductor dual-output boost converter is presented. This converter adopts a time-multiplexing control in providing two independent supply voltages using only one 1 /spl mu/H off-chip inductor. The topology could easily be extended to give multiple outputs. The converter is fabricated with a standard 0.5 /spl mu/m CMOS n-well process. At an oscillator frequency of 1 MHz, the conversion efficiency reaches 88% at a total output power of 350 mW.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126102140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
A variable gain IF amplifier with -67 dBc IM/sub 3/-distortion at 1.4 V/sub pp/ output in 0.25 /spl mu/m CMOS 一个可变增益中频放大器，在1.4 V/sub / pp/输出时具有-67 dBc的IM/sub - 3/-失真，采用0.25 /spl mu/m CMOS
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934202
K. Philips, E. Dijkmans
{"title":"A variable gain IF amplifier with -67 dBc IM/sub 3/-distortion at 1.4 V/sub pp/ output in 0.25 /spl mu/m CMOS","authors":"K. Philips, E. Dijkmans","doi":"10.1109/VLSIC.2001.934202","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934202","url":null,"abstract":"A variable gain amplifier based on feedback has IM/sub 3/-products below -67 dBc around the 10.7 MHz IF of an AM/FM radio receiver. It consumes 2.7 mA from a 2.5 V supply delivering a differential output signal of 1.4 V/sub pp/ with 96 dB dynamic range in a 9 kHz AM channel. The active area is 0.038 mm/sup 2/ in 0.25 /spl mu/m CMOS.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125397181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 66-400 MHz, adaptive-lock-mode DLL circuit with duty-cycle error correction [for SDRAMs] 带占空比纠错的66- 400mhz自适应锁模DLL电路[用于dram]
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934188
Y. Okuda, M. Horiguchi, Y. Nakagome
{"title":"A 66-400 MHz, adaptive-lock-mode DLL circuit with duty-cycle error correction [for SDRAMs]","authors":"Y. Okuda, M. Horiguchi, Y. Nakagome","doi":"10.1109/VLSIC.2001.934188","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934188","url":null,"abstract":"A DLL circuit featuring variable \"lock mode\" and correction of duty-cycle error is described. The DLL circuit has a wide locking range from under 66 MHz to 400 MHz. The chip area and power consumption at 400 MHz are 0.33 mm/sup 2/ and 24 mW, respectively.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122774938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Comparative performance, leakage power and switching power of circuits in 150 nm PD-SOI and bulk technologies including impact of SOI history effect 比较150nm PD-SOI和块体工艺电路的性能、漏功率和开关功率，包括SOI历史效应的影响
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934244
S. Narendra, J. Tschanz, A. Keshavarzi, S. Borkar, V. De
{"title":"Comparative performance, leakage power and switching power of circuits in 150 nm PD-SOI and bulk technologies including impact of SOI history effect","authors":"S. Narendra, J. Tschanz, A. Keshavarzi, S. Borkar, V. De","doi":"10.1109/VLSIC.2001.934244","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934244","url":null,"abstract":"History effect measurements on different circuits in a 150 nm SOI technology show no adverse impact on worst-case delay vs. leakage trade-offs. The performance advantage of SOI over bulk is shown to come mostly from capacitance reduction. Hence, it will diminish with technology scaling.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129562026","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
An SOI CMOS LVDS driver and receiver pair 一个SOI CMOS LVDS驱动器和接收器对
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934224
Brian Young
{"title":"An SOI CMOS LVDS driver and receiver pair","authors":"Brian Young","doi":"10.1109/VLSIC.2001.934224","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934224","url":null,"abstract":"A low-voltage differential signaling (LVDS) driver and receiver pair utilizing source-body-tied silicon-on-insulator CMOS transistors is shown to operate at 1 Gb/s data rates with zero bit error rate using a 2/sup 31/-1 pseudo-random bit sequence. For the driver, a level-shifter with gate voltage protection transitions from thin oxide core transistors to DGO output transistors was used. The receiver uses parallel PFET and NFET dual gate oxide transistors to enable common-mode input from 0-2.4 V.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121643878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Low power motion compensation block IP with embedded DRAM macro for portable multimedia applications 低功耗运动补偿块IP与嵌入式DRAM宏便携式多媒体应用
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934207
Chi-Weon Yoon, Jeonghoon Kook, Ramchan Woo, Se-Joong Lee, Kangmin Lee, H. Yoo
{"title":"Low power motion compensation block IP with embedded DRAM macro for portable multimedia applications","authors":"Chi-Weon Yoon, Jeonghoon Kook, Ramchan Woo, Se-Joong Lee, Kangmin Lee, H. Yoo","doi":"10.1109/VLSIC.2001.934207","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934207","url":null,"abstract":"A 16.3 mW low power motion compensation (MC) block IP with 1.25 Mbit embedded DRAM macro is implemented using 0.18 /spl mu/m EML technology for portable video applications. For low power consumption, its frequency is lowered to 20 MHz by utilizing parallelism in datapath. Embedded DRAM frame buffer eliminates external data I/O. In addition, distributed nine-tiled mapping (DNTM) with partial activation scheme reduces power for accessing the frame buffer up to 31% compared to conventional 1-bank tiled mapping. Adaptive fetch control (AFC) in data buffer reduces power up to 29% by eliminating unnecessary switching in datapath.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125834522","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A pixel-level automatic calibration circuit scheme for sensing initialization of a capacitive fingerprint sensor LSI 一种电容式指纹传感器LSI感测初始化的像素级自动校准电路方案
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934229
H. Morimura, S. Shigematsu, T. Shimamura, K. Machida, I. Kyuragi
{"title":"A pixel-level automatic calibration circuit scheme for sensing initialization of a capacitive fingerprint sensor LSI","authors":"H. Morimura, S. Shigematsu, T. Shimamura, K. Machida, I. Kyuragi","doi":"10.1109/VLSIC.2001.934229","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934229","url":null,"abstract":"We propose a pixel-level automatic calibration circuit scheme that initializes a capacitive fingerprint sensor LSI to eliminate the influence of the surface condition, which is degraded by dirt during practical use. The calibration is executed by adjusting the variable capacitance in each pixel to make the sensed signals of all pixels the same. A fingerprint sensor LSI using the 0.5-/spl mu/m CMOS process/sensor process demonstrates that clear fingerprint images are always obtained by the scheme though the surface condition degrades. The proposed scheme ensures consistent clear image capture during long-term usage.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128477120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Single-electron pass-transistor logic and its application to a binary adder 单电子通管逻辑及其在二进制加法器上的应用
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934196
Y. Ono, Y. Takahashi
{"title":"Single-electron pass-transistor logic and its application to a binary adder","authors":"Y. Ono, Y. Takahashi","doi":"10.1109/VLSIC.2001.934196","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934196","url":null,"abstract":"A new type of logic for constructing single-electron transistor (SET) circuits is proposed. The logic uses multigate SETs as pass transistors. The pass signals are routed with a small voltage so that the SETs can utilize Coulomb blockade effects. They are boosted at the output node when transferred to the input gates of other circuits. Since the multigate configuration enables us to implement XOR function using just one device, the logic can express sum- and carry-bits of an adder in a compact way. We have fabricated an elemental circuit of the logic and tested the basic operation of the SETs in the circuit. We also describe a multibit binary adder based on the logic, and discuss the circuit size and speed.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128529766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
On-die clock jitter detector for high speed microprocessors 用于高速微处理器的片上时钟抖动检测器
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934233
R. Kuppuswamy, K. Callahan, Keng L. Wong, D. Ratchen, G. Taylor
{"title":"On-die clock jitter detector for high speed microprocessors","authors":"R. Kuppuswamy, K. Callahan, Keng L. Wong, D. Ratchen, G. Taylor","doi":"10.1109/VLSIC.2001.934233","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934233","url":null,"abstract":"An on-die clock jitter detector has been designed for high speed microprocessor circuits and fabricated in 0.18 /spl mu/m CMOS technology. Variation of internal clock high/low time or period has been recorded. Innovative circuit techniques are used to provide fast initial DLL lock, adaptive filtering, granular jitter computation, and enhanced immunity to power-supply noise. It compares individual clock cycles to the average clock period, reporting the differences. The system has multiple output modes to allow more complete understanding of the jitter distribution and time dependence.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128678965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
A 0.9-/spl mu/A standby current DSP core using improved ABC-MT-CMOS with charge pump circuit 一个0.9-/spl mu/A待机电流DSP核心，采用改进的ABC-MT-CMOS带电荷泵电路
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934246
H. Notani, M. Koyama, R. Mano, H. Makjno, Y. Matsuda
{"title":"A 0.9-/spl mu/A standby current DSP core using improved ABC-MT-CMOS with charge pump circuit","authors":"H. Notani, M. Koyama, R. Mano, H. Makjno, Y. Matsuda","doi":"10.1109/VLSIC.2001.934246","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934246","url":null,"abstract":"A 64-bit 80-MHz multimedia DSP core has been designed using 0.15-/spl mu/m CMOS technology. An improved Auto-Backgate-Controlled MT-CMOS (ABC-MT-CMOS) circuit with a charge pump is adopted to suppress the standby leakage current. The dynamic active current of the whole chip was simulated to optimize the size of the switch for the power supply control. The DSP core chip, which integrated 300 kgate logic, 64-kbyte SRAM and charge pump circuit, has only 0.9-/spl mu/A standby leakage current.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131056970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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