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2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)最新文献

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A new column redundancy scheme for yield improvement of high speed DRAMs with multiple bit pre-fetch structure 一种提高多比特预取结构高速dram成成率的列冗余方案
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934198
Jae-Goo Lee, Young-Hyun Jun, K. Kyung, C. Yoo, Yong-Ho Cho, Sooin Cho
{"title":"A new column redundancy scheme for yield improvement of high speed DRAMs with multiple bit pre-fetch structure","authors":"Jae-Goo Lee, Young-Hyun Jun, K. Kyung, C. Yoo, Yong-Ho Cho, Sooin Cho","doi":"10.1109/VLSIC.2001.934198","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934198","url":null,"abstract":"A novel dual CSL column redundancy scheme (DCCR) that can improve effectiveness of repair and minimize overhead of die area is proposed. DCCR can repair failure bits of self-half I/O block by the unit of single bit, not by CSL. DCCR can also improve the data access speed by reducing the local I/O loading.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123259739","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A 6.25 ns random access 0.25 /spl mu/m embedded DRAM 6.25 ns随机存取0.25 /spl mu/m嵌入式DRAM
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934251
P. DeMone, M. Dunn, D. Haerle, Jin-Ki Kim, D. MacDonald, P. Nyasulu, D. Perry, S. Smith, T. Wojcicki, Zhouhong Zhang
{"title":"A 6.25 ns random access 0.25 /spl mu/m embedded DRAM","authors":"P. DeMone, M. Dunn, D. Haerle, Jin-Ki Kim, D. MacDonald, P. Nyasulu, D. Perry, S. Smith, T. Wojcicki, Zhouhong Zhang","doi":"10.1109/VLSIC.2001.934251","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934251","url":null,"abstract":"A new embedded DRAM architecture with uniform low latency operation was developed for computing, signal processing, and networking applications. Two hard macro blocks 104 K/spl times/24b and 104 K/spl times/16b, were implemented in a 0.25 micron stacked capacitor blended logic DRAM process. The combination of novel control architecture, circuit design, and physical implementation permitted a simulated worst case row access cycle time of 6.25 ns.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"415 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115982668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Parametric yield enhancement system via circuit level device optimization using statistical circuit simulation 利用统计电路仿真优化电路级器件的参数化良率增强系统
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934227
M. Miyama, S. Kamohara, K. Okuyama, Y. Oji
{"title":"Parametric yield enhancement system via circuit level device optimization using statistical circuit simulation","authors":"M. Miyama, S. Kamohara, K. Okuyama, Y. Oji","doi":"10.1109/VLSIC.2001.934227","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934227","url":null,"abstract":"To achieve high yield products without degrading the performance, it is important to optimize the device condition, considering the process variation. We present a model parameter extraction methodology to extract the process variation from the E-T (Electrical Test) data. We have estimated the parametric yield of a 0.20 /spl mu/m process SRAM test chip using Monte Carlo simulation and have obtained good agreement compared to measurement. We also performed device optimization using a critical path to improve the parametric yield.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121713008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Quasi-worst-condition built-in-self-test scheme for 4-Mb loadless CMOS four-transistor SRAM macro 4mb无负载CMOS四晶体管SRAM宏准最坏条件内置自检方案
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934248
K. Takeda, Y. Aimoto, K. Nakamura, S. Masuoka, K. Ishikawa, K. Noda, T. Takeshima, T. Murotani
{"title":"Quasi-worst-condition built-in-self-test scheme for 4-Mb loadless CMOS four-transistor SRAM macro","authors":"K. Takeda, Y. Aimoto, K. Nakamura, S. Masuoka, K. Ishikawa, K. Noda, T. Takeshima, T. Murotani","doi":"10.1109/VLSIC.2001.934248","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934248","url":null,"abstract":"We have developed a quasi-worst-condition Built-In-Self-Test (BIST) scheme capable of detecting defective cells. The effectiveness of the BIST, which is conducted at the time of power supply injection, is independent of ambient temperature. Measurement results indicate that defective cells detected in a wafer functional test in worst condition would also be detected with our newly developed BIST.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131525112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A cell transistor scalable array architecture for high-density DRAMs 用于高密度dram的单元晶体管可扩展阵列架构
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934185
D. Takashima, H. Nakano
{"title":"A cell transistor scalable array architecture for high-density DRAMs","authors":"D. Takashima, H. Nakano","doi":"10.1109/VLSIC.2001.934185","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934185","url":null,"abstract":"The limitation of DRAM cell transistor scalability is a severe problem in scaled DRAMs. A DRAM requires thicker gate oxide than that in logic LSIs, because a high wordline voltage must be applied to a memory cell transistor in order to write \"1\" data into the cell capacitor via the cell transistor. A new DRAM array architecture for scaled DRAMs is proposed. This scheme reduces stress bias for cell transistors, and enables the cell transistor to shrink without speed penalty.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114433295","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A system LSI memory redundancy technique using an ie-Flash (inverse-gate-electrode flash) programming circuit 一种采用ie-Flash(反栅极闪存)编程电路的系统LSI存储器冗余技术
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934199
M. Yamaoka, K. Yanagisawa, S. Shukuri, K. Norisue, K. Ishibashi
{"title":"A system LSI memory redundancy technique using an ie-Flash (inverse-gate-electrode flash) programming circuit","authors":"M. Yamaoka, K. Yanagisawa, S. Shukuri, K. Norisue, K. Ishibashi","doi":"10.1109/VLSIC.2001.934199","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934199","url":null,"abstract":"A new memory redundancy technique using ie-flash (inverse-gate-electrode flash) memory cells was developed. Ie-flash can be fabricated by the conventional logic CMOS process, so no additional processes are necessary to use it in system LSIs, and it can be programmed by logic tester. This new redundancy technique was successfully implemented in the cache memories of a 32-bit RISC microprocessor.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116959652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
An optimally coupled 5 GHz quadrature LC oscillator 一种最佳耦合5ghz正交LC振荡器
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934211
P. van de Ven, J. van der Tang, D. Kasperkovitz, A. V. van Roermund
{"title":"An optimally coupled 5 GHz quadrature LC oscillator","authors":"P. van de Ven, J. van der Tang, D. Kasperkovitz, A. V. van Roermund","doi":"10.1109/VLSIC.2001.934211","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934211","url":null,"abstract":"A 5 GHz quadrature LC oscillator is realized which is based on a new architecture for multi-phase LC oscillators. Each section in the oscillator is coupled with an explicit phase shift of 180 degrees divided by the number of sections. Analysis on behavioral level shows that this maximizes the quality factor, and as a result, the carrier-to-noise ratio and robustness. An effective quality factor is derived which quantizes the degradation in phase noise performance if the sections of a multiphase LC oscillator are non-optimally coupled. The realized 5 GHz quadrature LC oscillator demonstrates that even at high frequencies the additional complexity of the proposed architecture yields a CNR improvement. The oscillator is realized in a BiCMOS process with a cut-off frequency of 30 GHz using an LC resonator with a quality factor of 4. A tuning range from 4.91 to 5.23 GHz is obtained with a CNR better than 113 dBc/Hz at 2 MHz offset. The VCO core power dissipation is only 21.2 mW at 2.7 V supply voltage.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125717944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18 /spl mu/ 宇宙射线致静态锁存器软误差超过0.18 /spl mu/的标度趋势
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934195
T. Karnik, B. Bloechel, Krishnamurthy Soumyanath, Vivek De, S. Borkar
{"title":"Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18 /spl mu/","authors":"T. Karnik, B. Bloechel, Krishnamurthy Soumyanath, Vivek De, S. Borkar","doi":"10.1109/VLSIC.2001.934195","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934195","url":null,"abstract":"This paper describes an experiment to characterize soft error rate of static latches for neutrons using a neutron beam, with measured soft error rates as a function of diffusion collection areas and supply voltages. The paper also quantifies the effectiveness of two promising hardening techniques and scaling trends.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129527655","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 137
A micropower log-domain filter using enhanced lateral PNPs in a 0.25 /spl mu/m CMOS process 在0.25 /spl mu/m CMOS工艺中使用增强横向PNPs的微功率对数域滤波器
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934231
N. Krishnapura, Y. Tsividis
{"title":"A micropower log-domain filter using enhanced lateral PNPs in a 0.25 /spl mu/m CMOS process","authors":"N. Krishnapura, Y. Tsividis","doi":"10.1109/VLSIC.2001.934231","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934231","url":null,"abstract":"A 2/sup nd/ order low-pass log-domain filter is fabricated in a 0.25 /spl mu/m CMOS technology using enhanced lateral bipolar transistors. pMOS devices operating in accumulation are used for the integration capacitors. The filter when tuned to a bandwidth of 22 kHz, consumes 4.1 /spl mu/W from a 1.5 V supply and has an r.m.s. output noise of 0.25 nA. The filter's SNR at 1% THD is 56.1 dB and its maximum S/(N+THD) is 44.9 dB. The chip occupies 0.085 mm/sup 2/.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125618556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 50-MHz 98-dB dynamic-range dB-linear programmable-gain amplifier with 2-dB gain steps for 3-V power supply 50mhz 98 db动态范围db线性可编程增益放大器，具有2 db增益步长，适用于3v电源
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934200
K. Nah, Byeong-ha Park
{"title":"A 50-MHz 98-dB dynamic-range dB-linear programmable-gain amplifier with 2-dB gain steps for 3-V power supply","authors":"K. Nah, Byeong-ha Park","doi":"10.1109/VLSIC.2001.934200","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934200","url":null,"abstract":"A programmable-gain amplifier (PGA) circuit introduced in this paper has a dynamic gain range of 98-dB with 2-dB gain steps and is controlled by 6-bit gain control bits for a 3-V power supply. It has been fabricated in a 0.5-/spl mu/m 15-GHz f/sub T/ Si BiCMOS process and draws a constant current of 13-mA, independent of the gain settings. The active die area taken up by the circuit is 400-/spl mu/m /spl times/1170-/spl mu/m. A noise figure (NF) of 5-dB was measured at the maximum gain setting.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116295066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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