一种提高多比特预取结构高速dram成成率的列冗余方案

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI:10.1109/VLSIC.2001.934198

Jae-Goo Lee, Young-Hyun Jun, K. Kyung, C. Yoo, Yong-Ho Cho, Sooin Cho

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引用次数: 5

摘要

提出了一种新的双CSL柱冗余方案(DCCR)，以提高维修效率和减少模具面积开销。DCCR可以以单比特为单位修复自半I/O块的故障位，而不能以CSL为单位修复。DCCR还可以通过减少本地I/O负载来提高数据访问速度。

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A new column redundancy scheme for yield improvement of high speed DRAMs with multiple bit pre-fetch structure

A novel dual CSL column redundancy scheme (DCCR) that can improve effectiveness of repair and minimize overhead of die area is proposed. DCCR can repair failure bits of self-half I/O block by the unit of single bit, not by CSL. DCCR can also improve the data access speed by reducing the local I/O loading.

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来源期刊

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

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