A new column redundancy scheme for yield improvement of high speed DRAMs with multiple bit pre-fetch structure

Abstract

A novel dual CSL column redundancy scheme (DCCR) that can improve effectiveness of repair and minimize overhead of die area is proposed. DCCR can repair failure bits of self-half I/O block by the unit of single bit, not by CSL. DCCR can also improve the data access speed by reducing the local I/O loading.