A micropower log-domain filter using enhanced lateral PNPs in a 0.25 /spl mu/m CMOS process

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI:10.1109/VLSIC.2001.934231

N. Krishnapura, Y. Tsividis

引用次数: 8

Abstract

A 2/sup nd/ order low-pass log-domain filter is fabricated in a 0.25 /spl mu/m CMOS technology using enhanced lateral bipolar transistors. pMOS devices operating in accumulation are used for the integration capacitors. The filter when tuned to a bandwidth of 22 kHz, consumes 4.1 /spl mu/W from a 1.5 V supply and has an r.m.s. output noise of 0.25 nA. The filter's SNR at 1% THD is 56.1 dB and its maximum S/(N+THD) is 44.9 dB. The chip occupies 0.085 mm/sup 2/.

查看原文本刊更多论文

在0.25 /spl mu/m CMOS工艺中使用增强横向PNPs的微功率对数域滤波器

采用增强型横向双极晶体管，以0.25 /spl μ m CMOS技术制备了2/sup /阶低通对数域滤波器。聚积式pMOS器件用于集成电容器。当调谐到22 kHz带宽时，滤波器的功耗为4.1 /spl mu/W，来自1.5 V电源，有效值输出噪声为0.25 nA。该滤波器在1% THD时的信噪比为56.1 dB，最大S/(N+THD)为44.9 dB。芯片占用0.085 mm/sup 2/。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

自引率

0.00%

发文量