4mb无负载CMOS四晶体管SRAM宏准最坏条件内置自检方案

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI:10.1109/VLSIC.2001.934248

K. Takeda, Y. Aimoto, K. Nakamura, S. Masuoka, K. Ishikawa, K. Noda, T. Takeshima, T. Murotani

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引用次数: 2

摘要

我们开发了一种能够检测缺陷细胞的准最坏条件内置自检(BIST)方案。BIST的有效性是在电源注入时进行的，与环境温度无关。测量结果表明，在最坏条件下晶圆功能测试中检测到的缺陷细胞也可以用我们新开发的BIST检测到。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Quasi-worst-condition built-in-self-test scheme for 4-Mb loadless CMOS four-transistor SRAM macro

We have developed a quasi-worst-condition Built-In-Self-Test (BIST) scheme capable of detecting defective cells. The effectiveness of the BIST, which is conducted at the time of power supply injection, is independent of ambient temperature. Measurement results indicate that defective cells detected in a wafer functional test in worst condition would also be detected with our newly developed BIST.

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2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

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