6.25 ns随机存取0.25 /spl mu/m嵌入式DRAM

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI:10.1109/VLSIC.2001.934251

P. DeMone, M. Dunn, D. Haerle, Jin-Ki Kim, D. MacDonald, P. Nyasulu, D. Perry, S. Smith, T. Wojcicki, Zhouhong Zhang

{"title":"6.25 ns随机存取0.25 /spl mu/m嵌入式DRAM","authors":"P. DeMone, M. Dunn, D. Haerle, Jin-Ki Kim, D. MacDonald, P. Nyasulu, D. Perry, S. Smith, T. Wojcicki, Zhouhong Zhang","doi":"10.1109/VLSIC.2001.934251","DOIUrl":null,"url":null,"abstract":"A new embedded DRAM architecture with uniform low latency operation was developed for computing, signal processing, and networking applications. Two hard macro blocks 104 K/spl times/24b and 104 K/spl times/16b, were implemented in a 0.25 micron stacked capacitor blended logic DRAM process. The combination of novel control architecture, circuit design, and physical implementation permitted a simulated worst case row access cycle time of 6.25 ns.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"415 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 6.25 ns random access 0.25 /spl mu/m embedded DRAM\",\"authors\":\"P. DeMone, M. Dunn, D. Haerle, Jin-Ki Kim, D. MacDonald, P. Nyasulu, D. Perry, S. Smith, T. Wojcicki, Zhouhong Zhang\",\"doi\":\"10.1109/VLSIC.2001.934251\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new embedded DRAM architecture with uniform low latency operation was developed for computing, signal processing, and networking applications. Two hard macro blocks 104 K/spl times/24b and 104 K/spl times/16b, were implemented in a 0.25 micron stacked capacitor blended logic DRAM process. The combination of novel control architecture, circuit design, and physical implementation permitted a simulated worst case row access cycle time of 6.25 ns.\",\"PeriodicalId\":346869,\"journal\":{\"name\":\"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)\",\"volume\":\"415 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2001.934251\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2001.934251","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

为计算、信号处理和网络应用开发了一种具有统一低延迟操作的新型嵌入式DRAM架构。两个硬宏块104 K/spl times/24b和104 K/spl times/16b在0.25微米堆叠电容混合逻辑DRAM工艺中实现。新型控制体系结构、电路设计和物理实现的结合允许模拟最坏情况下的行访问周期时间为6.25 ns。

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A 6.25 ns random access 0.25 /spl mu/m embedded DRAM

A new embedded DRAM architecture with uniform low latency operation was developed for computing, signal processing, and networking applications. Two hard macro blocks 104 K/spl times/24b and 104 K/spl times/16b, were implemented in a 0.25 micron stacked capacitor blended logic DRAM process. The combination of novel control architecture, circuit design, and physical implementation permitted a simulated worst case row access cycle time of 6.25 ns.

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来源期刊

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

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