2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)最新文献

筛选
英文 中文
Dynamically reconfigurable logic LSI-PCA-1 动态可重构逻辑LSI-PCA-1
Hideyuki Ito, Ryusuke Konishi, H. Nakada, Hideyuki Tsuboi, Y. Okuyama, A. Nagoya
{"title":"Dynamically reconfigurable logic LSI-PCA-1","authors":"Hideyuki Ito, Ryusuke Konishi, H. Nakada, Hideyuki Tsuboi, Y. Okuyama, A. Nagoya","doi":"10.1109/VLSIC.2001.934208","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934208","url":null,"abstract":"This paper describes the realization of a dynamically reconfigurable logic LSI based on a novel parallel computer architecture. The key point of the architecture is its dual-structured cell array to enable dynamic and autonomous reconfiguration of the logic circuit. The LSI was completed with successful introduction of two specific features: fully asynchronous logic circuits and homogeneous structure using only LUTs.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127927876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Full-CMOS 2.4 GHz wideband CDMA transmitter and receiver with direct conversion mixers and DC-offset cancellation 全cmos 2.4 GHz宽带CDMA发射机和接收机与直接转换混频器和直流偏移抵消
Kangyoon Lee, Seungwooi Lee, Y. Koo, Hyoung-Ki Huh, H. Nam, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, D. Jeong, Wonchan Kim
{"title":"Full-CMOS 2.4 GHz wideband CDMA transmitter and receiver with direct conversion mixers and DC-offset cancellation","authors":"Kangyoon Lee, Seungwooi Lee, Y. Koo, Hyoung-Ki Huh, H. Nam, Jeongwoo Lee, Joonbae Park, Kyeongho Lee, D. Jeong, Wonchan Kim","doi":"10.1109/VLSIC.2001.934177","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934177","url":null,"abstract":"The proposed direct conversion scheme combined with a multi-phase sampling fractional-N prescaler offers solutions to problems of a direct conversion transmitter and receiver. In the experimental results, the transmitter shows 0 dBm maximum output power with 38 dB ACPR at 0.5 BW, 50 dB dynamic range, and 363 mW power consumption. The receiver shows -115.4 dBm sensitivity, 4.0 dB noise figure, and 80 dB dynamic range with 396 mW power consumption.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127721103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Silicon integrated high performance inductors in a 0.18 /spl mu/m CMOS technology for MMIC 用于MMIC的0.18 /spl μ m CMOS技术的硅集成高性能电感
H. Hsu, Jiong-Guang Su, Shyh-Chyi Wong, Yuan-Chen Sun, Chun-Yen Chang, Tiao-Yuan Huang, Chi-Chong Tsai, Ching-Lun Lin, R. S. Liou, Ruey-Wen Chang, Ta-Hsun Yeh, Che-Sheng Chen, Chih-Wen Huang, Hsiang-Lin Huang, Ching-Wei Chen
{"title":"Silicon integrated high performance inductors in a 0.18 /spl mu/m CMOS technology for MMIC","authors":"H. Hsu, Jiong-Guang Su, Shyh-Chyi Wong, Yuan-Chen Sun, Chun-Yen Chang, Tiao-Yuan Huang, Chi-Chong Tsai, Ching-Lun Lin, R. S. Liou, Ruey-Wen Chang, Ta-Hsun Yeh, Che-Sheng Chen, Chih-Wen Huang, Hsiang-Lin Huang, Ching-Wei Chen","doi":"10.1109/VLSIC.2001.934237","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934237","url":null,"abstract":"This paper presents a complete portfolio of silicon integrated inductors in a 0.18 μm CMOS technology. In addition to inductor design, we also present a complete optimization methodology with associated modeling and key characterization. Our inductor quality factors have been enhanced by optimizing patterned ground shield and taper coils or using copper metallization. The quality-factor peak can further be optimized at an application-specific frequency band with our optimization algorithm. To facilitate IC design with inductors, a novel model considering eddy current loss was developed, Finally, to integrate inductors into a system-chip, inductor-to-inductor and substrate-inductor coupling were investigated.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127469849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Autonomous decentralized low-power system LSI using self-instructing predictive shutdown method 采用自指示预测关断方法的自主分散低功耗系统LSI
T. Shimizu, F. Arakawa, T. Kawahara
{"title":"Autonomous decentralized low-power system LSI using self-instructing predictive shutdown method","authors":"T. Shimizu, F. Arakawa, T. Kawahara","doi":"10.1109/VLSIC.2001.934193","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934193","url":null,"abstract":"There is a strong demand from the mobile telecommunications industry for LSIs that achieve higher performance using less power. However, it is almost impossible in a short design period for a circuit designer to carry out an optimal design with both the power and performance items of a LSI having tens of millions of logic gates. Furthermore, a considerable component of the DC-leakage current originates from the subthreshold, gate leakage, and junction leakage currents of the MOS transistor even when the LSI is in an active state. This paper proposes an autonomous decentralized system LSI where each block has a predictive shutdown function using an MOS power switch controlled by a method based on self-instruction.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134590537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A pulse-tuned charge controlling scheme for uniform main and reference bitline voltage generation on ITIC FeRAM 一种用于ITIC FeRAM主位线和基准位线电压均匀产生的脉冲调谐电荷控制方案
H. Kang, H. Kye, D. Kim, Geun-Il Lee, Je-Hoon Park, J. Wee, Seaung-Suk Lee, S. Hong, N. Kang, Jin-Yong Chung
{"title":"A pulse-tuned charge controlling scheme for uniform main and reference bitline voltage generation on ITIC FeRAM","authors":"H. Kang, H. Kye, D. Kim, Geun-Il Lee, Je-Hoon Park, J. Wee, Seaung-Suk Lee, S. Hong, N. Kang, Jin-Yong Chung","doi":"10.1109/VLSIC.2001.934215","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934215","url":null,"abstract":"In order to improve cell array efficiency and reference voltage characteristics of ITlC FeRAM, two key techniques are proposed in this paper. 1) Cell operation scheme with pulse-tuned signals on wordline and plateline for achieving uniform bitline levels in short time and 2) reference voltage generation scheme using dual pulse control for reference voltage to track variable bitline sensing voltage in wide range of operation voltage and temperature. 2Mb ITlC FeRAM in unit block of 512 rows by 256 columns cell array with 0.35pm design rule are implemented. The optimized uniform bitline sensing voltage and reference voltage are achieved at the condition of the first wordline pulse signal of 3011s and the reference dual pulse signal time of 30-4011s at 3V in room temperature.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116401688","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Design and characterization of vertical mesh capacitors in standard CMOS 标准CMOS中垂直网状电容器的设计与表征
K. T. Christensen
{"title":"Design and characterization of vertical mesh capacitors in standard CMOS","authors":"K. T. Christensen","doi":"10.1109/VLSIC.2001.934238","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934238","url":null,"abstract":"This paper shows how good RF capacitors can be made in a standard digital CMOS process. The capacitors which are also well suited for binary weighted switched capacitor banks show very good RF performance: Q-values of 57 at 4.0 GHz, a density of 0.27 fF//spl mu/2, 2.2 /spl mu/m wide shielded unit capacitors, 6% bottom plate capacitance, better than 3-5% process variation and negligible series inductance. Further, a simple yet accurate method is presented that allows hand calculation of the capacitance value.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"77 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117063736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Two schemes to reduce interconnect delay in bi-directional and uni-directional buses 两种减少双向和单向总线互连延迟的方案
K. Nose, T. Sakurai
{"title":"Two schemes to reduce interconnect delay in bi-directional and uni-directional buses","authors":"K. Nose, T. Sakurai","doi":"10.1109/VLSIC.2001.934235","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934235","url":null,"abstract":"As the device dimension is scaled down, interconnect RC delay becomes dominant performance limiter in high-performance VLSIs. Another issue in the submicron interconnects is a drastic increase of coupling capacitance due to the higher aspect ratio to reduce the interconnect resistance. The increase of the coupling capacitance degrades signal integrity, inducing noise problems and delay fluctuation problems. Buffer insertion (repeater insertion) is one of the most effective ways to decrease the interconnect delay. The original buffer insertion, however, cannot be applied to bi-directional buses because the buffer is uni-directional in nature. Some circuit configurations that can be applied to bi-directional buses have been proposed. These circuits turn out to be prone to malfunctions when there is a noise from adjacent lines in scaled down interconnect systems where capacitive coupling is large. A new buffer insertion scheme for bi-directional buses, namely the dual-rail bus (DRB) scheme, which does not have noise problems is proposed and measured in this paper. Another proposal is on a high-speed buffer insertion scheme for uni-directional buses by making use of staggered firing. The staggered firing bus (SFIB) is proposed and measured.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126577760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Digital vision chips and high-speed vision systems 数字视觉芯片和高速视觉系统
M. Ishikawa, T. Komuro
{"title":"Digital vision chips and high-speed vision systems","authors":"M. Ishikawa, T. Komuro","doi":"10.1109/VLSIC.2001.934175","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934175","url":null,"abstract":"Conventional image processing has a critical limit of frame rate derived from serial transmission of the video signal. In order to overcome the limit, fully parallel processing architecture without scanning has been proposed. In this paper, vision chips with digital circuits and high speed application systems developed in our laboratory are described.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"274 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134212100","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
480 ps 64-bit race logic adder 480ps 64位竞争逻辑加法器
Se-Joong Lee, Ramchan Woo, H. Yoo
{"title":"480 ps 64-bit race logic adder","authors":"Se-Joong Lee, Ramchan Woo, H. Yoo","doi":"10.1109/VLSIC.2001.934183","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934183","url":null,"abstract":"In this paper, a high-speed 64-bit carry look-ahead adder is implemented by race logic for fast carry generation. G/sup 1/g/G/sup 1/k (Level 1 Group Generate/Kill) and G/sup 2/g/G/sup 2/k (Level 2 Group Generate/Kill) stages are designed by race logic. The adder consists of 4-stages, and clk-S63 delay is 480 ps with 0.18 /spl mu/m CMOS technology.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132791025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
ASIC design methodology with on-demand library generation 按需生成库的ASIC设计方法
H. Onodera, M. Hashimoto, T. Hashimoto
{"title":"ASIC design methodology with on-demand library generation","authors":"H. Onodera, M. Hashimoto, T. Hashimoto","doi":"10.1109/VLSIC.2001.934194","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934194","url":null,"abstract":"This paper describes a custom design method of ASICs with on-demand library generation. According to the result of performance estimation, a tailored library is generated and supplied to cell-based design tools. A symbolic layout system that produces a cell layout with variable driving strength is developed. The tunability can be utilized for generating a rich set of driving strength as well as design optimization in post-layout stage. Design experiments and measured performance of a fabricated chip demonstrate the effectiveness of the proposed approach.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114901053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信