480ps 64位竞争逻辑加法器

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI:10.1109/VLSIC.2001.934183

Se-Joong Lee, Ramchan Woo, H. Yoo

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引用次数: 8

摘要

为了快速生成进位，本文采用竞争逻辑实现了一种高速64位进位预判加法器。G/sup 1/ G/ G/sup 1/k(一级组生成/杀死)和G/sup 2/ G/ G/sup 2/k(二级组生成/杀死)阶段是根据种族逻辑设计的。加法器由4级组成，时钟- s63延迟为480 ps，采用0.18 /spl mu/m CMOS技术。

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480 ps 64-bit race logic adder

In this paper, a high-speed 64-bit carry look-ahead adder is implemented by race logic for fast carry generation. G/sup 1/g/G/sup 1/k (Level 1 Group Generate/Kill) and G/sup 2/g/G/sup 2/k (Level 2 Group Generate/Kill) stages are designed by race logic. The adder consists of 4-stages, and clk-S63 delay is 480 ps with 0.18 /spl mu/m CMOS technology.

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2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

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