Digital vision chips and high-speed vision systems

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI:10.1109/VLSIC.2001.934175

M. Ishikawa, T. Komuro

引用次数: 29

Abstract

Conventional image processing has a critical limit of frame rate derived from serial transmission of the video signal. In order to overcome the limit, fully parallel processing architecture without scanning has been proposed. In this paper, vision chips with digital circuits and high speed application systems developed in our laboratory are described.

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数字视觉芯片和高速视觉系统

由于视频信号的串行传输，传统的图像处理具有帧率的临界限制。为了克服这一限制，提出了一种无需扫描的全并行处理架构。本文介绍了本实验室研制的具有数字电路的视觉芯片和高速应用系统。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

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