Silicon integrated high performance inductors in a 0.18 /spl mu/m CMOS technology for MMIC

Abstract

This paper presents a complete portfolio of silicon integrated inductors in a 0.18 μm CMOS technology. In addition to inductor design, we also present a complete optimization methodology with associated modeling and key characterization. Our inductor quality factors have been enhanced by optimizing patterned ground shield and taper coils or using copper metallization. The quality-factor peak can further be optimized at an application-specific frequency band with our optimization algorithm. To facilitate IC design with inductors, a novel model considering eddy current loss was developed, Finally, to integrate inductors into a system-chip, inductor-to-inductor and substrate-inductor coupling were investigated.