{"title":"标准CMOS中垂直网状电容器的设计与表征","authors":"K. T. Christensen","doi":"10.1109/VLSIC.2001.934238","DOIUrl":null,"url":null,"abstract":"This paper shows how good RF capacitors can be made in a standard digital CMOS process. The capacitors which are also well suited for binary weighted switched capacitor banks show very good RF performance: Q-values of 57 at 4.0 GHz, a density of 0.27 fF//spl mu/2, 2.2 /spl mu/m wide shielded unit capacitors, 6% bottom plate capacitance, better than 3-5% process variation and negligible series inductance. Further, a simple yet accurate method is presented that allows hand calculation of the capacitance value.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"77 2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"Design and characterization of vertical mesh capacitors in standard CMOS\",\"authors\":\"K. T. Christensen\",\"doi\":\"10.1109/VLSIC.2001.934238\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper shows how good RF capacitors can be made in a standard digital CMOS process. The capacitors which are also well suited for binary weighted switched capacitor banks show very good RF performance: Q-values of 57 at 4.0 GHz, a density of 0.27 fF//spl mu/2, 2.2 /spl mu/m wide shielded unit capacitors, 6% bottom plate capacitance, better than 3-5% process variation and negligible series inductance. Further, a simple yet accurate method is presented that allows hand calculation of the capacitance value.\",\"PeriodicalId\":346869,\"journal\":{\"name\":\"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)\",\"volume\":\"77 2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2001.934238\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2001.934238","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and characterization of vertical mesh capacitors in standard CMOS
This paper shows how good RF capacitors can be made in a standard digital CMOS process. The capacitors which are also well suited for binary weighted switched capacitor banks show very good RF performance: Q-values of 57 at 4.0 GHz, a density of 0.27 fF//spl mu/2, 2.2 /spl mu/m wide shielded unit capacitors, 6% bottom plate capacitance, better than 3-5% process variation and negligible series inductance. Further, a simple yet accurate method is presented that allows hand calculation of the capacitance value.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
