2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)最新文献

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P-boosted source followers: a robust energy-efficient bus driver technique p增强源跟踪器:一种鲁棒节能总线驱动技术
R. Krishnamurthy, K. Soumyanath, D. Ayers
{"title":"P-boosted source followers: a robust energy-efficient bus driver technique","authors":"R. Krishnamurthy, K. Soumyanath, D. Ayers","doi":"10.1109/VLSIC.2001.934234","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934234","url":null,"abstract":"This paper describes a PMOS-boosted source follower bus driver technique for robust, full-swing, on-chip buses. A 10% performance improvement on a 128-bit L1 cache bus is achieved on a 0.18 /spl mu/m production 64-bit processor. A regional clock grid driver scheme with 14% energy reduction is also described.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126615843","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 1 GHz power efficient single chip multiprocessor system for broadband networking applications 一种用于宽带网络应用的1 GHz节能单芯片多处理器系统
S. Santhanam, R. Allmon, K. Anne, R. Blake, Nils Bunger, Brian Campbell, M. Carlson, Zongjian Chen, Jeff Cheng, T. Do, D. Dobberpuhl, J. Ingino, D. Kidd, David Kruckemyer, J. Lee, D. Murray, S. Nishimoto, L. O'Donnell, Maksim Oykher, Mukaya Panich, M. Pearce, D. Priore, D. Rodriguez, R. Rogenmoser, Dongwook Suh, Venkatesh Sundaresan, E. Supnet, V. V. Kaenel, Gary W Yee, G. Yiu, C. Vo, R. Wen
{"title":"A 1 GHz power efficient single chip multiprocessor system for broadband networking applications","authors":"S. Santhanam, R. Allmon, K. Anne, R. Blake, Nils Bunger, Brian Campbell, M. Carlson, Zongjian Chen, Jeff Cheng, T. Do, D. Dobberpuhl, J. Ingino, D. Kidd, David Kruckemyer, J. Lee, D. Murray, S. Nishimoto, L. O'Donnell, Maksim Oykher, Mukaya Panich, M. Pearce, D. Priore, D. Rodriguez, R. Rogenmoser, Dongwook Suh, Venkatesh Sundaresan, E. Supnet, V. V. Kaenel, Gary W Yee, G. Yiu, C. Vo, R. Wen","doi":"10.1109/VLSIC.2001.934209","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934209","url":null,"abstract":"The Broadcom BCM12500 is a high performance system on a chip (SOC) targeted at network centric tasks. The chip consists of two high performance SB-1 MIPS64/sup TM/ CPUs, a shared 512 KB L2 cache, a DDR memory controller, and integrated I/O. All major blocks of the processor are connected together via the ZBbus/sup TM/; a high speed split transaction fully coherent multi processor bus. Three Gigabit Ethernet MACs enable a direct interface to network elements. High-speed system I/O is provided using AMD's Lightning Data Transport (LDT/sup TM/) I/O fabric and a 66 MHz PCI bus. The die measures 14.2 mm by 13.3 mm in a bulk 0.15 /spl mu/m CMOS technology and has a power dissipation of 13 W at 1.2 V and 1 GHz.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"45 22","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113936923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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