A 1 GHz power efficient single chip multiprocessor system for broadband networking applications

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI:10.1109/VLSIC.2001.934209

S. Santhanam, R. Allmon, K. Anne, R. Blake, Nils Bunger, Brian Campbell, M. Carlson, Zongjian Chen, Jeff Cheng, T. Do, D. Dobberpuhl, J. Ingino, D. Kidd, David Kruckemyer, J. Lee, D. Murray, S. Nishimoto, L. O'Donnell, Maksim Oykher, Mukaya Panich, M. Pearce, D. Priore, D. Rodriguez, R. Rogenmoser, Dongwook Suh, Venkatesh Sundaresan, E. Supnet, V. V. Kaenel, Gary W Yee, G. Yiu, C. Vo, R. Wen

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引用次数: 7

Abstract

The Broadcom BCM12500 is a high performance system on a chip (SOC) targeted at network centric tasks. The chip consists of two high performance SB-1 MIPS64/sup TM/ CPUs, a shared 512 KB L2 cache, a DDR memory controller, and integrated I/O. All major blocks of the processor are connected together via the ZBbus/sup TM/; a high speed split transaction fully coherent multi processor bus. Three Gigabit Ethernet MACs enable a direct interface to network elements. High-speed system I/O is provided using AMD's Lightning Data Transport (LDT/sup TM/) I/O fabric and a 66 MHz PCI bus. The die measures 14.2 mm by 13.3 mm in a bulk 0.15 /spl mu/m CMOS technology and has a power dissipation of 13 W at 1.2 V and 1 GHz.

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一种用于宽带网络应用的1 GHz节能单芯片多处理器系统

Broadcom BCM12500是一款针对网络中心任务的高性能片上系统(SOC)。该芯片由两个高性能的SB-1 MIPS64/sup TM/ cpu、一个共享的512 KB二级缓存、一个DDR内存控制器和集成I/O组成。处理器各主要模块通过ZBbus/sup TM/连接在一起;一种高速分割事务全相干多处理器总线。三个千兆以太网mac可以直接连接到网络元素。高速系统I/O使用AMD的闪电数据传输(LDT/sup TM/) I/O结构和66 MHz PCI总线提供。该芯片尺寸为14.2 mm × 13.3 mm，采用0.15 /spl mu/m CMOS技术，在1.2 V和1ghz下功耗为13w。

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2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

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