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2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)最新文献

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Robustness of sub-70 nm dynamic circuits: analytical techniques and scaling trends 70纳米以下动态电路的鲁棒性:分析技术和标度趋势
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934181
M. Anders, R. Krishnamurthy, R. Spotten, K. Soumyanath
{"title":"Robustness of sub-70 nm dynamic circuits: analytical techniques and scaling trends","authors":"M. Anders, R. Krishnamurthy, R. Spotten, K. Soumyanath","doi":"10.1109/VLSIC.2001.934181","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934181","url":null,"abstract":"We present an accurate (to within 3%, across two process generations), three parameter, closed form, time-domain technique for evaluating the noise response of domino circuits. We evaluate the robustness of scaled topologies to show that conventional domino circuits will cease to be useful around the 70 nm generation. The paper concludes with possible device/circuit approaches to extend domino circuit usefulness.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"27 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133002698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
A 1 V operational, 20 MS/s and 57 dB of S/N, current-mode CMOS sample-and-hold IC 工作电压为1v, s /s为20ms /s, s /N为57db，电流模式CMOS采样保持IC
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934240
Y. Sugimoto
{"title":"A 1 V operational, 20 MS/s and 57 dB of S/N, current-mode CMOS sample-and-hold IC","authors":"Y. Sugimoto","doi":"10.1109/VLSIC.2001.934240","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934240","url":null,"abstract":"A 1 V operational, 20 MS/s MOS sample-and-hold IC, which is applicable to video signal processing, has been developed. The signal-to-noise ratio (SNR) reached 57 dB under the application of +200 μA of differential input signal current at a 1 MHz frequency. The fabrication process was 0.35 μm CMOS with a threshold voltage of +0.35 V for an NMOS device and -0.35 V for a PMOS device.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128742109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 0.6-V voltage reference circuit based on /spl Sigma/-V/sub TH/ architecture in CMOS/SIMOX 基于CMOS/SIMOX /spl Sigma/-V/sub - TH/架构的0.6 v电压基准电路
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934220
M. Ugajin, T. Tsukahara
{"title":"A 0.6-V voltage reference circuit based on /spl Sigma/-V/sub TH/ architecture in CMOS/SIMOX","authors":"M. Ugajin, T. Tsukahara","doi":"10.1109/VLSIC.2001.934220","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934220","url":null,"abstract":"A voltage reference circuit based on threshold-voltage-summation (/spl Sigma/-V/sub TH/) architecture is proposed. Its output (V/sub REF/) is not affected by the input offset of the feedback amplifier in the circuit. Thus, its V/sub REF/ dispersion is considerably reduced. A prototype circuit fabricated in fully depleted CMOS/SIMOX technology can operate at a supply voltage as low as 0.6 V. The measured V/sub REF/ is 530 mV/spl plusmn/16.8 mV (30) and the measured temperature coefficient is 0.02 mV//spl deg/C/spl plusmn/0.0G mV//spl deg/C (3/spl sigma/).","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133894019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 2 GHz merged CMOS LNA and mixer for WCDMA 用于WCDMA的2 GHz合并CMOS LNA和混频器
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934180
Ali Sjöland, Henrik Abidi, Ali Karimi-Sanjaani, liknrik Sjold, Asad A Abidi
{"title":"A 2 GHz merged CMOS LNA and mixer for WCDMA","authors":"Ali Sjöland, Henrik Abidi, Ali Karimi-Sanjaani, liknrik Sjold, Asad A Abidi","doi":"10.1109/VLSIC.2001.934180","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934180","url":null,"abstract":"A merged LNA and mixer with an on-chip VCO is fabricated in 0.35 /spl mu/m CMOS for a 2.1 GHz WCDMA receiver. The front-end consumes 8 mA from 2.7 V and gives NF of 3.2 dB, conversion gain of 24.2 dB, and input IP3 of -1.5 dBm. The VCO consumes 3 mA while achieving phase noise of -128.4 and -138.5 dBc/Hz at offsets of 5 and 15 MHz, respectively.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"4 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132768160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
A 1.8 GHz CMOS VCO with reduced phase noise 1.8 GHz CMOS压控振荡器，相位噪声降低
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934213
P. Andreani, H. Sjoland
{"title":"A 1.8 GHz CMOS VCO with reduced phase noise","authors":"P. Andreani, H. Sjoland","doi":"10.1109/VLSIC.2001.934213","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934213","url":null,"abstract":"A 2 V, 6 mA, 15% tuning range, 1.8 GHz VCO implemented in a standard 0.35 /spl mu/m CMOS process is presented. The phase noise of the VCO has been greatly reduced by means of on-chip filters and one off-chip low frequency inductor. The phase noise measured at 3 MHz offset from the carrier is between -141.5 dBc/Hz and -138.5 dBc/Hz over the whole tuning range.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133282459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Automatic calibration of modulated /spl Sigma/-/spl Delta/ frequency synthesizers 自动校准调制/spl Sigma/-/spl Delta/频率合成器
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934192
D. McMahill, C. Sodini
{"title":"Automatic calibration of modulated /spl Sigma/-/spl Delta/ frequency synthesizers","authors":"D. McMahill, C. Sodini","doi":"10.1109/VLSIC.2001.934192","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934192","url":null,"abstract":"This paper describes a sigma-delta (/spl Sigma/-/spl Delta/) synthesizer for Gaussian frequency and minimum shift keying (GFSK/GMSK) modulation. The key innovation is an in-service automatic calibration circuit which tunes the phase locked loop (PLL) to compensate for process tolerance and temperature variation. The PLL, including 1.8 GHz voltage controlled oscillator (VCO), /spl Sigma/-/spl Delta/ modulator, and calibration circuit has been implemented in a 0.6 micron BiCMOS integrated circuit. The test chip achieves 2.5 Mbit/second using GFSK and 5.0 Mbit/second using 4-FSK.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114082454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A bit-line GND sense technique for low-voltage operation FeRAM 一种用于低电压工作FeRAM的位线接地检测技术
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934216
S. Kawashima, T. Endo, T. Yamamoto, K. Nakabayashi, M. Nakazawa, K. Morita, M. Aoki
{"title":"A bit-line GND sense technique for low-voltage operation FeRAM","authors":"S. Kawashima, T. Endo, T. Yamamoto, K. Nakabayashi, M. Nakazawa, K. Morita, M. Aoki","doi":"10.1109/VLSIC.2001.934216","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934216","url":null,"abstract":"We propose a sense scheme in which a pMOS charge-transfer maintains the bit-line level near the GND level when the plate line goes high. The scheme supplies 0.5 V higher read-out voltages across the cell capacitors and achieves a 0.4 V higher differential amplitude in a 512-cell per bit-line structure than a conventional DRAM sense scheme. A shifted bias plate line layout enables a minimum number of bit-lines to be activated and achieves 8.06 mW at 3 V, 5 MHz, about same power as a conventional device.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115386128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An 8-GHz bandwidth 1-GS/s GaAs HBT dual track-and-hold 8ghz带宽1-GS/s GaAs HBT双跟踪保持
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934243
J.P.A. van der Wagt, M. Teshome
{"title":"An 8-GHz bandwidth 1-GS/s GaAs HBT dual track-and-hold","authors":"J.P.A. van der Wagt, M. Teshome","doi":"10.1109/VLSIC.2001.934243","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934243","url":null,"abstract":"A track-and-hold is a critical sub-circuit of a wideband pipelined ADC. A 1-GS/s fully differential dual track-and-hold circuit fabricated in an 80-GHz f/sub T//fax, GaAs HBT production process exhibits an input bandwidth of 8.4 GHz (0.5 V/sub pp/) and 9.3 GHz (small signal). Total harmonic distortion is -59 dB for 1-Vpp 1-GHz input, and -42 dB for 0.5-V/sub pp/ 5-GHz input. The chip occupies 0.9 mm/spl times/1.8 mm active area and consumes 2.2 W from /spl plusmn/5 V.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"321 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132269947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Concurrent dual-band CMOS low noise amplifiers and receiver architectures 并发双频CMOS低噪声放大器和接收器架构
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934254
H. Hashemi, A. Hajimiri
{"title":"Concurrent dual-band CMOS low noise amplifiers and receiver architectures","authors":"H. Hashemi, A. Hajimiri","doi":"10.1109/VLSIC.2001.934254","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934254","url":null,"abstract":"A new concurrent dual-band receiver architecture is introduced that is capable of simultaneous operation at two different frequency bands. The concurrent operation results in higher bandwidth, lower total power dissipation and less sensitivity to channel variations. The architecture uses a novel concurrent dual-band low noise amplifier (LNA), combined with an elaborate frequency conversion scheme to reject the image bands. A general methodology for the design of concurrent LNAs is provided that makes it possible to achieve simultaneous narrowband gain and matching at multiple frequencies. The methodology is demonstrated by implementing an integrated dual-band concurrent LNA using 0.35 /spl mu/m CMOS transistors. The LNA provides narrow-band gain and matching at 2.45 GHz and 5.25 GHz bands, simultaneously. It drains 4 mA of current and achieves voltage gains of 14 dB and 15.5 dB, input return losses of 25 dB and 15 dB, and noise figures of 2.3 dB and 4.5 dB at these two bands, respectively.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125650936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 99
A highly-tunable 12 GHz quadrature LC-VCO in SiGe BiCMOS process 基于SiGe BiCMOS工艺的高可调谐12ghz正交LC-VCO
2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI: 10.1109/VLSIC.2001.934212
A. L. Coban, K. Ahmed, C. Chang
{"title":"A highly-tunable 12 GHz quadrature LC-VCO in SiGe BiCMOS process","authors":"A. L. Coban, K. Ahmed, C. Chang","doi":"10.1109/VLSIC.2001.934212","DOIUrl":"https://doi.org/10.1109/VLSIC.2001.934212","url":null,"abstract":"This paper describes a 12 GHz fully-integrated, fully-differential quadrature LC VCO. Fabricated in a 0.35 /spl mu/m SiGe BiCMOS process with 55 GHz f/sub T/, the oscillator achieves 37% tuning range (9.62 to 14.0 GHz) and exhibits 113.5 and -112.3 dBc/Hz phase noise at 10 MHz away from 11 and 13 GHz oscillation frequencies, respectively. The oscillator draws 39 mA current from a 3.3 V supply and occupies 0.36 mm/sup 2/ active die area.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117042954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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