一种用于低电压工作FeRAM的位线接地检测技术

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI:10.1109/VLSIC.2001.934216

S. Kawashima, T. Endo, T. Yamamoto, K. Nakabayashi, M. Nakazawa, K. Morita, M. Aoki

{"title":"一种用于低电压工作FeRAM的位线接地检测技术","authors":"S. Kawashima, T. Endo, T. Yamamoto, K. Nakabayashi, M. Nakazawa, K. Morita, M. Aoki","doi":"10.1109/VLSIC.2001.934216","DOIUrl":null,"url":null,"abstract":"We propose a sense scheme in which a pMOS charge-transfer maintains the bit-line level near the GND level when the plate line goes high. The scheme supplies 0.5 V higher read-out voltages across the cell capacitors and achieves a 0.4 V higher differential amplitude in a 512-cell per bit-line structure than a conventional DRAM sense scheme. A shifted bias plate line layout enables a minimum number of bit-lines to be activated and achieves 8.06 mW at 3 V, 5 MHz, about same power as a conventional device.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A bit-line GND sense technique for low-voltage operation FeRAM\",\"authors\":\"S. Kawashima, T. Endo, T. Yamamoto, K. Nakabayashi, M. Nakazawa, K. Morita, M. Aoki\",\"doi\":\"10.1109/VLSIC.2001.934216\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We propose a sense scheme in which a pMOS charge-transfer maintains the bit-line level near the GND level when the plate line goes high. The scheme supplies 0.5 V higher read-out voltages across the cell capacitors and achieves a 0.4 V higher differential amplitude in a 512-cell per bit-line structure than a conventional DRAM sense scheme. A shifted bias plate line layout enables a minimum number of bit-lines to be activated and achieves 8.06 mW at 3 V, 5 MHz, about same power as a conventional device.\",\"PeriodicalId\":346869,\"journal\":{\"name\":\"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2001.934216\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2001.934216","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 2

摘要

我们提出了一种传感方案，其中pMOS电荷转移在板线变高时保持位线水平接近地电平。与传统的DRAM感测方案相比，该方案在单元电容器上提供高0.5 V的读出电压，并在512单元/位线结构中实现高0.4 V的差分幅度。移位偏置板线布局使激活的位线数量最少，在3 V, 5 MHz时达到8.06 mW，与传统器件的功率大致相同。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A bit-line GND sense technique for low-voltage operation FeRAM

We propose a sense scheme in which a pMOS charge-transfer maintains the bit-line level near the GND level when the plate line goes high. The scheme supplies 0.5 V higher read-out voltages across the cell capacitors and achieves a 0.4 V higher differential amplitude in a 512-cell per bit-line structure than a conventional DRAM sense scheme. A shifted bias plate line layout enables a minimum number of bit-lines to be activated and achieves 8.06 mW at 3 V, 5 MHz, about same power as a conventional device.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

自引率

0.00%

发文量