A cell transistor scalable array architecture for high-density DRAMs

Abstract

The limitation of DRAM cell transistor scalability is a severe problem in scaled DRAMs. A DRAM requires thicker gate oxide than that in logic LSIs, because a high wordline voltage must be applied to a memory cell transistor in order to write "1" data into the cell capacitor via the cell transistor. A new DRAM array architecture for scaled DRAMs is proposed. This scheme reduces stress bias for cell transistors, and enables the cell transistor to shrink without speed penalty.