Quasi-worst-condition built-in-self-test scheme for 4-Mb loadless CMOS four-transistor SRAM macro

Abstract

We have developed a quasi-worst-condition Built-In-Self-Test (BIST) scheme capable of detecting defective cells. The effectiveness of the BIST, which is conducted at the time of power supply injection, is independent of ambient temperature. Measurement results indicate that defective cells detected in a wafer functional test in worst condition would also be detected with our newly developed BIST.