A 66-400 MHz, adaptive-lock-mode DLL circuit with duty-cycle error correction [for SDRAMs]

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI:10.1109/VLSIC.2001.934188

Y. Okuda, M. Horiguchi, Y. Nakagome

引用次数: 7

Abstract

A DLL circuit featuring variable "lock mode" and correction of duty-cycle error is described. The DLL circuit has a wide locking range from under 66 MHz to 400 MHz. The chip area and power consumption at 400 MHz are 0.33 mm/sup 2/ and 24 mW, respectively.

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带占空比纠错的66- 400mhz自适应锁模DLL电路[用于dram]

介绍了一种具有可变“锁模”和占空比误差校正功能的动态链接电路。DLL电路具有从66兆赫到400兆赫的宽锁定范围。400 MHz时的芯片面积和功耗分别为0.33 mm/sup /和24 mW。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

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