低功耗运动补偿块IP与嵌入式DRAM宏便携式多媒体应用

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI:10.1109/VLSIC.2001.934207

Chi-Weon Yoon, Jeonghoon Kook, Ramchan Woo, Se-Joong Lee, Kangmin Lee, H. Yoo

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引用次数: 4

摘要

采用0.18 /spl mu/m EML技术，实现了一个16.3 mW低功耗运动补偿(MC)块IP和1.25 Mbit嵌入式DRAM宏，用于便携式视频应用。为了降低功耗，利用数据路径的并行性将其频率降低到20 MHz。嵌入式DRAM帧缓冲器消除了外部数据I/O。此外，与传统的1-bank平铺映射相比，采用部分激活方案的分布式9平铺映射(DNTM)可将访问帧缓冲区的功耗降低31%。数据缓冲区中的自适应读取控制(AFC)通过消除数据路径中不必要的切换，可减少高达29%的功率。

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Low power motion compensation block IP with embedded DRAM macro for portable multimedia applications

A 16.3 mW low power motion compensation (MC) block IP with 1.25 Mbit embedded DRAM macro is implemented using 0.18 /spl mu/m EML technology for portable video applications. For low power consumption, its frequency is lowered to 20 MHz by utilizing parallelism in datapath. Embedded DRAM frame buffer eliminates external data I/O. In addition, distributed nine-tiled mapping (DNTM) with partial activation scheme reduces power for accessing the frame buffer up to 31% compared to conventional 1-bank tiled mapping. Adaptive fetch control (AFC) in data buffer reduces power up to 29% by eliminating unnecessary switching in datapath.

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2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

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