一个0.9-/spl mu/A待机电流DSP核心，采用改进的ABC-MT-CMOS带电荷泵电路

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI:10.1109/VLSIC.2001.934246

H. Notani, M. Koyama, R. Mano, H. Makjno, Y. Matsuda

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引用次数: 1

摘要

采用0.15-/spl mu/m CMOS技术设计了64位80 mhz多媒体DSP内核。采用带电荷泵的改进型Auto-Backgate-Controlled MT-CMOS (ABC-MT-CMOS)电路抑制待机漏电流。通过对整个芯片的动态有功电流进行仿真，优化开关尺寸，实现电源控制。该DSP核心芯片集成了300kgate逻辑、64kbyte SRAM和电荷泵电路，待机漏电流仅为0.9-/spl mu/A。

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A 0.9-/spl mu/A standby current DSP core using improved ABC-MT-CMOS with charge pump circuit

A 64-bit 80-MHz multimedia DSP core has been designed using 0.15-/spl mu/m CMOS technology. An improved Auto-Backgate-Controlled MT-CMOS (ABC-MT-CMOS) circuit with a charge pump is adopted to suppress the standby leakage current. The dynamic active current of the whole chip was simulated to optimize the size of the switch for the power supply control. The DSP core chip, which integrated 300 kgate logic, 64-kbyte SRAM and charge pump circuit, has only 0.9-/spl mu/A standby leakage current.

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2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

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