采用多电压SOI CMOS技术的低功耗lsi 0.5 V供电方案

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185) Pub Date : 2001-06-14 DOI:10.1109/VLSIC.2001.934245

T. Fuse, A. Kameyama, M. Ohta, K. Ohuchi

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引用次数: 17

摘要

介绍了一种适用于0.5V工作lsi的新型供电方案。该系统包含效率超过90%的片上降压dc-dc变换器、0.5V工作逻辑、待机模式下保持数据的100MHz工作F/F和双轨电平变换器。采用0.35/spl mu/m多vt SOI CMOS工艺制备的dc-dc变换器TEG，在0.5V/10mW输出下实现了稳定的回收特性和92%的末级效率。

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A 0.5 V power-supply scheme for low power LSIs using multi-Vt SOI CMOS technology

Describes a novel power-supply scheme suitable for 0.5V operating LSIs. The system contains the on-chip buck dc-dc converter with over-90% efficiency, 0.5V operating logic, 100MHz operating F/Fs with holding data in the stand-by mode, and the dual-rail level converter. The dc-dc converter TEG, fabricated using 0.35/spl mu/m multi-Vt SOI CMOS process, realized stable recovery characteristics and a final stage efficiency of 92% with 0.5V/10mW output.

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来源期刊

2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)

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