A. Alvandpour, R. Krishnamurthy, K. Soumyanath, S. Borkar
{"title":"低于0.13/spl亩/宽的动态门的条件看守技术","authors":"A. Alvandpour, R. Krishnamurthy, K. Soumyanath, S. Borkar","doi":"10.1109/VLSIC.2001.934184","DOIUrl":null,"url":null,"abstract":"Increasing leakage currents seriously limits the robustness of wide dynamic gates. We present an efficient, conditional keeper technique, where a large fraction of the keeper is turned ON only if the dynamic output remains high in the evaluation phase. Thus, strong keepers can be utilized with leaky gates without significant impact on performance of the gates. Compared to the conventional technique, 9-to-35% higher performances have been observed across 8-to-32-bit wide dynamic gates in a 0.13 /spl mu/m technology.","PeriodicalId":346869,"journal":{"name":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-06-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"42","resultStr":"{\"title\":\"A conditional keeper technique for sub-0.13/spl mu/ wide dynamic gates\",\"authors\":\"A. Alvandpour, R. Krishnamurthy, K. Soumyanath, S. Borkar\",\"doi\":\"10.1109/VLSIC.2001.934184\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Increasing leakage currents seriously limits the robustness of wide dynamic gates. We present an efficient, conditional keeper technique, where a large fraction of the keeper is turned ON only if the dynamic output remains high in the evaluation phase. Thus, strong keepers can be utilized with leaky gates without significant impact on performance of the gates. Compared to the conventional technique, 9-to-35% higher performances have been observed across 8-to-32-bit wide dynamic gates in a 0.13 /spl mu/m technology.\",\"PeriodicalId\":346869,\"journal\":{\"name\":\"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-06-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"42\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2001.934184\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2001.934184","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A conditional keeper technique for sub-0.13/spl mu/ wide dynamic gates
Increasing leakage currents seriously limits the robustness of wide dynamic gates. We present an efficient, conditional keeper technique, where a large fraction of the keeper is turned ON only if the dynamic output remains high in the evaluation phase. Thus, strong keepers can be utilized with leaky gates without significant impact on performance of the gates. Compared to the conventional technique, 9-to-35% higher performances have been observed across 8-to-32-bit wide dynamic gates in a 0.13 /spl mu/m technology.