A conditional keeper technique for sub-0.13/spl mu/ wide dynamic gates

Abstract

Increasing leakage currents seriously limits the robustness of wide dynamic gates. We present an efficient, conditional keeper technique, where a large fraction of the keeper is turned ON only if the dynamic output remains high in the evaluation phase. Thus, strong keepers can be utilized with leaky gates without significant impact on performance of the gates. Compared to the conventional technique, 9-to-35% higher performances have been observed across 8-to-32-bit wide dynamic gates in a 0.13 /spl mu/m technology.