2016 International Conference on Electronics Packaging (ICEP)最新文献_第5页

Thermal compression bonding for power IC attachment using pure Zn 纯锌用于功率IC附件的热压缩键合

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486858

Chih-Hao Fan, Ting-Jui Wu, Jenn-Ming Song

{"title":"Thermal compression bonding for power IC attachment using pure Zn","authors":"Chih-Hao Fan, Ting-Jui Wu, Jenn-Ming Song","doi":"10.1109/ICEP.2016.7486858","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486858","url":null,"abstract":"This study developed a low temperature solid-state direct bonding process for dissimilar metals. Experimental results show that Cu/Zn can be bonded successfully at 200°C under the loading of 10MPa for 30 minutes. The joints thus formed exhibited a shear strength up to 20MPa. If the thermal compression was performed at 300°C, the shear strength of bonded Cu/Zn and Cu/Ni/Zn joints exceeded 50MPa, especially for Cu/Zn joint, the strength even reached 70MPa. With respect to high temperature mechanical properties, due to the softening of Zn, the shear strength of all the joints decreased with a higher testing temperature. During aging at 250°C, the shear strength of Cu/Zn degraded drastically up to 500hr and after that the joint strength remained almost constant. The strength of Cu/Ni/Zn joints decreased gradually and maintained 30MPa for 500hr. The shear strength of both of the joints tended to be identical subjected to aging for 800hr. The deterioration of the joint strength during aging can be ascribed to the competitive growth between CuZn5 and Cu5Zn8 resulting in collapse and oxidation of CuZn5. The electroplated Ni and Ni5Zn21 thus formed can retard the excessive growth of Cu5Zn8 to some extent.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131002786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Non-destructive testing method for chip warpage -Applications of synchrotron radiation X-ray 芯片翘曲的无损检测方法。同步辐射x射线的应用

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486772

H. Hsu, Chang-meng Wang, Hsin-yi Lee, A. Wu

引用次数: 0

The advantage of Slow Cure NCP in filp chip package 慢固化NCP在芯片封装中的优势

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486904

Yoshihide Fukuhara, M. Hoshiyama, Toshikazu Hocchi, Y. Kamata, Hirotatsu Ikarashi, Ruka Iwaya

引用次数: 0

Using FEA to determine test speed for high speed shear test on BGA based on field conditions 基于现场条件，采用有限元法确定了BGA高速剪切试验的试验速度

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486844

C. Selvanayagam

{"title":"Using FEA to determine test speed for high speed shear test on BGA based on field conditions","authors":"C. Selvanayagam","doi":"10.1109/ICEP.2016.7486844","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486844","url":null,"abstract":"Miniaturization and increased functionality has been the trend in the mobile electronic device industry. Inevitably, the drive for increased density of miniaturized components has led to the miniaturization of the BGA joints. Smaller joints, in general, have shorter lives as the crack propagation path is shorter. The high speed shear test is gaining popularity as a component-level test to ensure good outgoing solder joints. One advantage of this test over the static shear test is that higher test speeds induce brittle failure in the intermetallic layer (IMC) of the joint, similar to that in drop impact. As a result, this test can detect variations in substrate finishing quality and joint reflow conditions that could lead to premature drop impact failures. However, selection of test speed is critical. The general consensus is to test at the speed where IMC failures are induced. With recent advances in pad finishing and solder alloys resulting in thinner and more uniform IMC layers, testing at a speed where IMC failures occur could result in over-testing the device, well beyond the strain rates experienced in the field. This, in turn, would lead to the over-design of solder joints. Clearly, a method to determine equivalent shear test speed is required, where strain rates during shear test are matched to that in field conditions. This work presents a methodology to determine the equivalent shear test speed for high speed shear test based on shock and vibration requirements. FEA is used to match the maximum strain rates during the most severe impact or vibration application of the device to that during high speed shear test. Usage of the methodology is demonstrated on a board with a BGA component under three different drop conditions. Results show that for the three drop conditions, the equivalent shear speed is lower than 200mm/s. Given that the maximum capability of the tester is 4m/s, shear speed for high speed shear test needs to be selected carefully.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122807681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Stress evaluation of flip chip bonding die by thermal compression bonding using Raman spectroscopy 热压缩键合倒装片键合模的拉曼光谱应力评估

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486870

Mototaka Ito, T. Uchida, R. Sugie

引用次数: 0

Novel copper surface preparation processes for copper alloy lead frame lamination pretreatment in embedded packaging device 嵌入式封装装置中铜合金引线框架层压预处理的新型铜表面制备工艺

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486883

Wei-chung Chen, C. Lee, Lu-Fu Lin, Yen-Fu Liu, H. Cheng, T.-J Hsu, Kun-Ting Tsai, Ming-Hung Chen, Tang-Yuan Chen, P. Yang, S. Uegaki, C. Hung

引用次数: 0

Warpage characterization analysis for Embedded package technology 嵌入式封装技术翘曲特性分析

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486881

Tang-Yuan Chen, M. Shih, Ming-Hung Chen, Wei-chung Chen, S. Uegaki, C. Kao, Ping-Feng Yang, C. Hung

{"title":"Warpage characterization analysis for Embedded package technology","authors":"Tang-Yuan Chen, M. Shih, Ming-Hung Chen, Wei-chung Chen, S. Uegaki, C. Kao, Ping-Feng Yang, C. Hung","doi":"10.1109/ICEP.2016.7486881","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486881","url":null,"abstract":"The Embedded die in substrate (EDS) market has grown significantly over the past several years and it is now one of the fastest growing packaging technologies in the semiconductor industry driven by smaller form factor, better heat dissipating, low noise emission, higher levels of integration and better performance. In addition, for power management and mobile-wireless application the embedded technology had been evaluated to replace assembles fabrication not only thinner thickness but superior electrical performance. However, Embedded Die causes severe package warpage issue due to CTE mismatch happened on diffusion bond process. In this work, the three Dimensional Warpage Metrology Analyzer (3D-WMA), as a non-contact optical deformation measurement method used to measure unit package warpage behavior with different temperatures. Reducing the warpage issue of package, the parametric factors on the structure and material would be investigated. These design guides are then studied by finite element modeling to understand mechanism for warpage improvement and the dielectric material property selection is critically factoring for warpage control. The measured warpage data agrees very well with the predicted one that the maximum discrepancy is within 3%. Based on the above justification, it starts to carry out the parametric study. Initially, changed prepreg can improve the warpage 64%. Besides, Cu layer should be thick and soldermask layer should be thin. Furthermore, asymmetric structure design of Cu layer and soldermask layer is another effective for warpage reduction. Impact from structural design and material property selection is studied in this paper.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114309587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Three-dimensional integration technology of separate SOI layers for photodetectors and signal processors of CMOS image sensors 光电探测器和CMOS图像传感器信号处理器分离SOI层的三维集成技术

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486785

M. Goto, K. Hagiwara, Y. Honda, M. Nanba, Y. Iguchi, T. Saraya, M. Kobayashi, E. Higurashi, H. Toshiyoshi, T. Hiramoto

引用次数: 1

A built-in electrical test circuit for detecting open leads in assembled PCB circuits 一种内置的电气测试电路，用于检测组装的PCB电路中的开路引线

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486867

Takumi Miyabe, M. Hashizume, H. Yotsuyanagi, Shyue-Kung Lu, Z. Roth

引用次数: 1

Characterization of elastic-plastic properties of intermetallic compounds 金属间化合物弹塑性性能的表征

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486829

Ruei-You Hong, Hsien-Chie Cheng, Hsuan-Chi Hu, Wen-Hwa Chen

引用次数: 4