2016 International Conference on Electronics Packaging (ICEP)最新文献_第10页

Power cycling test and failure mode analysis of high-power module 大功率模块的功率循环试验及失效模式分析

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486850

L. Liao, Chun-Kai Liu, K. Chiang

引用次数: 4

Study on current and junction temperature stress aging effect for accelerated aging test of Light emitting diodes 发光二极管加速老化试验中电流和结温应力老化效应的研究

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486783

Chih-Ju Chan, Feng-Mao Hsu, Yen-Fu Su, K. Chiang

{"title":"Study on current and junction temperature stress aging effect for accelerated aging test of Light emitting diodes","authors":"Chih-Ju Chan, Feng-Mao Hsu, Yen-Fu Su, K. Chiang","doi":"10.1109/ICEP.2016.7486783","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486783","url":null,"abstract":"In recent years, Light emitting diodes (LEDs) has become more and more popular because of their low power consumption, low-pollution and long-life. Currently, the common lumen maintenance test of LED follows IES LM80-08 standard, which costs at least 6000 hours for measurement and prolongs the time-to-market schedule. In our previous researches, a modified accelerated aging test algorithm using different high temperature stress without input current was successfully proposed. And through the experiment, it shows that the modified accelerated aging test algorithm, which derived from Arrhenius equation, cannot fit the lifetime of LEDs aging in temperature and current stress. It recommends that the life prediction model has to make consideration of both heat and current. First of all, we need to measure the lumen maintenance in same junction temperature with different current. In this research we will use a validated finite element model and use thermal resistance of LED to predict the junction temperature of chip under different current input. And use the forward voltage method to measure the junction temperature to validate the simulation result and calculation result. During the experiment we found out the heating type and the size of oven will influence junction temperature of LED seriously. We need to consider about the oven when conducting aging test of LED in the future to make sure whether the measured result is correct. In summary, we found out the corresponding relation between current and ambient temperature for same junction temperature and oven's effect for junction temperature measurement. It would provide some considerations to the accelerated aging test with developed degradation prediction model in the future.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127672873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

VUV/O3 assisted single crystal quartz bonding with amorphous SiO2 intermedicate layer for manufacturing optical low pass filter VUV/O3辅助单晶石英与无定形SiO2中间层键合制备光学低通滤波器

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486866

Bo Ma, H. Kuwae, A. Okada, Weixin Fu, S. Shoji, J. Mizuno

引用次数: 2

Bonding process without pressure using a chestnut-burr-like particle paste for power electronics 电力电子用栗子毛刺状颗粒糊状物无压力粘合过程

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486854

Myong-Hoon Roh, H. Nishikawa, S. Tsutsumi, Naruhiko Nishiwaki, K. Ito, Koji Ishikawa, A. Katsuya, N. Kamada, M. Saito

{"title":"Bonding process without pressure using a chestnut-burr-like particle paste for power electronics","authors":"Myong-Hoon Roh, H. Nishikawa, S. Tsutsumi, Naruhiko Nishiwaki, K. Ito, Koji Ishikawa, A. Katsuya, N. Kamada, M. Saito","doi":"10.1109/ICEP.2016.7486854","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486854","url":null,"abstract":"High-lead-containing solder has been pushed to the limit of high-temperature stability and eco-friendly technology for next-generation power electronic devices. Silver is an attractive material as alternative of high-lead solder due to its high melting point and good electrical and thermal properties. However, silver nanoparticle paste is high cost, and contains a number of organic materials such as solvent and dispersants. These tend to produce unexpected large voids in the sintered layer after heating, and this affects the properties and reliability of devices. In this study, silver pastes composed only micro-sized particles were used for joints and a bonding without applied pressure was tried. Chestnut-burr-like silver particles was prepared for bonding without pressure and the effect of addition of small and spherical silver particles on bondability was investigated. The addition of spherical particles in chestnut-burr-like particle paste was promoted the sintering behavior. The joint using mixed silver particle with the weight ration of 5:5 showed the shear strength of 18.6 MPa, which was comparable to those of silver nanoparticle pastes by pressureless process.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131323323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

An overview of the Photonics Systems Manufacturing Consortium - A participant in the americal institute for manufacturing-integrated photonics institute 光子系统制造联盟概述-美国制造集成光子研究所的参与者

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486788

Richard Otte, R. Pfahl, L. Kimerling, B. Bottoms, J. MacWilliams, Rich Grzybowski, R. Kirchain, E. Olivetti

{"title":"An overview of the Photonics Systems Manufacturing Consortium - A participant in the americal institute for manufacturing-integrated photonics institute","authors":"Richard Otte, R. Pfahl, L. Kimerling, B. Bottoms, J. MacWilliams, Rich Grzybowski, R. Kirchain, E. Olivetti","doi":"10.1109/ICEP.2016.7486788","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486788","url":null,"abstract":"The evolution of the Photonics Systems Manufacturing Consortium (PSMC) and its activities and tentative results are discussed. The PSMC evolved from the long standing optical electronic roadmap activities of the Massachusetts Institute of Technology Micro Photonics Center Communications Technology Roadmap (MIT MPC CTR) and the international Network for Manufacturing Innovation (iNEMI) when these two organization jointly responded to and won a National Institute for Standards and Technology (NIST) RFQ to roadmap photonic integrated circuits and applications in May of 2014. PSMC has made much progress reported herein since then. In July of 2015, the formation of the American Institute for Manufacturing Integrated Photonics (AIM-IP) was announced. Subsequently, PSMC joined AIM-IP and is now expanding its role to include more applications of optical electronics technology. In addition, PSMC is running a series of workshops and seminars to gather information, in the first case, and to educate interested parties in the second case. The near term PSMC objective is to define gaps and technical needs in optical electronic that are, or will become, barriers to utilizing optical technologies in applications. The tentative results as of early December 2015 are reported as well as the intended activities over the next few years. The long term PSMC objective is to contribute to the AIM IP purpose of establishing a self-sustaining institution based on fulfilling the technology needs to enable the growth of optical electronics in data communications, sensors and other applications.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129740618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low temperature interconnect fabrication on PDMS polymeric substrates using Ag nanoparticles and submicron particles 利用银纳米粒子和亚微米粒子在PDMS聚合物衬底上制备低温互连

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486802

Sin-Yong Liang, Yu Fang, Po-Hao Chiang, Jenn-Ming Song, Lung-Tai Chen

{"title":"Low temperature interconnect fabrication on PDMS polymeric substrates using Ag nanoparticles and submicron particles","authors":"Sin-Yong Liang, Yu Fang, Po-Hao Chiang, Jenn-Ming Song, Lung-Tai Chen","doi":"10.1109/ICEP.2016.7486802","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486802","url":null,"abstract":"Taking the advantage of low sintering temperature and high processing flexibility, metallic nanoparticles (NPs) have been widely used to fabricate interconnections. To obtain excellent electrical conductivity, the surfactants protecting the nanoparticles have to be removed thermally and thus the particles can be well linked. Considering the interconnect fabrication on flexible substrates (usually polymers and papers) utilizing roll-to-roll technique, low processing temperature, short heating time or localized heating is required. By doing so, heat damages of the substrates and components can be prevented. Considering the application as interconnections for wearable electronics, this study develops a low-temperature chemical reduction process for the fabrication of conductive circuits on PDMS (Polydimethylsiloxane) substrate using carboxylate-capped Ag nanoparticles. Ag nanoparticle sintering can be achieved by soaking the nanoparticle deposits in a gentle reductive solution even at room temperature. Surface roughening treatment is performed to enhance the adhesion between conductive films and the substrate. The results of reliability tests demonstrate that the higher the bending deformation (curvature), a greater the electrical resistance for the conductive films. As for bending fatigue (shear strain: 0.25), the electrical performance of the flexible interconnections deteriorates in the first 300 bending cycles mainly due to the formation of crevices. It is interesting that after that the electrical resistance remains almost constant up to 1000 bending cycles. In addition, a novel interconnect fabrication method using Ag submicron particles will also be introduced in this report.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132058708","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Viscoelastic analysis of multistage stacked via structure in build-up substrate 堆砌衬底中多级叠孔结构的粘弹性分析

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486887

Hideaki Nagaoka, T. Akahoshi, Masaharu Furuyama, D. Mizutani

引用次数: 0

How the mold compound thermal expansion overrules the solder composition choice in board level reliability performance 模具复合热膨胀在板级可靠性性能中如何超越焊料成分的选择

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486790

B. Vandevelde, L. Degrendele, M. Cauwe, B. Allaert, R. Lauwaert, G. Willems

引用次数: 1

Transmission model of Human Body Communication incorporating size and distance between the two electrodes of a transmitter 包含发射器两个电极之间的尺寸和距离的人体通信传输模型

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486869

N. Arai, D. Muramatsu, K. Sasaki

引用次数: 3

Comparison of thermal stress concentration and profile between power cycling test and thermal cycling test for power device heat dissipation structures using Ag sintering chip-attachment 采用Ag烧结贴片的功率器件散热结构功率循环试验与热循环试验的热应力集中与分布比较

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486906

Kensuke Osonoe, Takahiro Asai, M. Aoki, Hitoshi Kida, N. Nakano

{"title":"Comparison of thermal stress concentration and profile between power cycling test and thermal cycling test for power device heat dissipation structures using Ag sintering chip-attachment","authors":"Kensuke Osonoe, Takahiro Asai, M. Aoki, Hitoshi Kida, N. Nakano","doi":"10.1109/ICEP.2016.7486906","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486906","url":null,"abstract":"Power semiconductor device technology needs highly efficient heat dissipation system having a chip bonding layer with high thermal conductance and reliability. This work clarifies 3D thermal stress profiles under power cycling test (PCT) and thermal cycling test (TCT) with multi-physics solver for the system having Ag sintered bonding layer as a new chip attachment technology. Both reliability test results on Von Mises stress profile are compared and the key features for each test are made clear. It was found that the maximum stress values within Si chip and Ag sintered bonding layer are at the corner of bonding layer for both PCT and TCT. The maximum stress of bonding layer under PCT ON state at chip power of 400 W is lower than the value under TCT with Ta of 25 °C which is the Ta of PCT. Under PCT the temperature difference from stress free temperature (Tr) for bonding layer is smaller than that under TCT with Ta of 25 °C, and this results in lower thermal stress in bonding layer. The maximum stress value of Ag sintered layer is a little lower than the conventional solder value under both PCT and TCT. This smaller stress of Ag sintered layer is thought to be due to lower Young's modulus of the Ag sintered layer.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130864152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4