{"title":"No pumping at 450°C with electrodeposited copper TSV","authors":"K. Kondo","doi":"10.1109/ECTC.2016.337","DOIUrl":"https://doi.org/10.1109/ECTC.2016.337","url":null,"abstract":"1.The additive A shows no pumping with electrodeposited copper TSV. 2. The resistivity of electrodeposited copper TSV after 450°C annealing for the wiring is only 1.09 of conventional electrodeposited copper. 3.The 34% TEC reduction has been realized at 230°C for solder reflow temperature for PCB. The 34% reduction has been obtained after the second annealing after 200°C, 60min with the additive B. 4.The resistivity of PCB copper after annealing is only 1.32 of conventional electrodeposited copper.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-08-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124501111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Libot, L. Arnaud, O. Dalverny, J. Alexis, P. Milesi, F. Dulondel
{"title":"Mechanical fatigue assessment of SAC305 solder joints under harmonic vibrations","authors":"J. Libot, L. Arnaud, O. Dalverny, J. Alexis, P. Milesi, F. Dulondel","doi":"10.1109/ICEP.2016.7486818","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486818","url":null,"abstract":"Vibration-induced solder joint fatigue is a main reliability concern for aerospace and military industries whose electronic equipment used in the field is required to remain functional under such loading. Due to the RoHS directive which eventually will prevent lead from being utilized in electronic systems, there is a need for a better understanding of lead-free mechanical behavior under vibration conditions. This study reports the durability of Sn3.0Ag0.5Cu (SAC305) solder joints subjected to harmonic solicitations at three specific temperatures (-55°C, 20°C and 105°C). A test assembly is designed and consists in a single daisy-chained 1152 I/O ball grid array (FBGA1152) package assembled on a flame retardant (FR-4) printed circuit board (PCB). The vibration levels are imposed by a controlled deflection at the center of the board at its natural frequency. The electric continuity is monitored to determine the number of cycles to failure of each sample. Mode shape measurements with a scanning vibrometer are also conducted and correlated with Finite Element Analysis (FEA) to ensure accurate calculation of stress within the critical solder balls at the corners of the component. The failed specimens are then cross-sectioned in order to determine failure modes. A comparison of SAC305 durability with SnPb36Ag2 solder is given, along with a set of lifetime measurements for two complementary assemblies: 68 I/O Leadless Chip Carrier (LCC68) and 324 I/O Plastic Ball Grid Array (PBGA324). It turns out that SAC305 outperforms SnPb36Ag2 and the effect of temperature on the mechanical durability of SAC305 appears to be minor. Failure analysis points out different failure modes such as ductile and brittle cracks at the interface between the solder bulk and the component, along with pad cratering-induced copper trace failures. FEA calculations provide data to estimate the high cycle fatigue (HCF) behavior of SAC305 solder under harmonic vibrations.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121586571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tomohiro Yamada, Shota Zempo, F. Koshiji, K. Koshiji
{"title":"Broadband antenna with asymmetrical radiating elements for cognitive radio system","authors":"Tomohiro Yamada, Shota Zempo, F. Koshiji, K. Koshiji","doi":"10.1109/ICEP.2016.7486913","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486913","url":null,"abstract":"In recent years, cognitive radio system has been receiving particular attention as a promising technology in order to materialize efficient network access. In this paper, heightening upper limit frequency of the wideband antenna for cognitive radio system was investigated by employing three types of the antenna element variations. As a result, the antenna with the VSWR less than 2.0, employing asymmetrical elements, was obtained in the frequency range of 3.1 GHz to 18 GHz. Although the radiation patterns were slightly distorted, it was acceptable in practical use.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121153352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High resolution printing processes with high throughput, enhanced step coverage, and high design flexibility","authors":"Y. Kusaka, H. Ushijima","doi":"10.1109/ICEP.2016.7486794","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486794","url":null,"abstract":"Reverse offset printing and microcontact printing are fascinating methods for fabricating fine patterns because both of them can attain a 1-μm/1-μm line-and-space resolution, and the resulting patterns manifest uniform layer-thicknesses irrespective of the pattern sizes. However, the printed pattern has very sharp edges; therefore, the step-coverage of subsequent overlying layers has often been a severe problem. Further, as reverse offset printing and microcontact printing use an engraved glass and a stamp, respectively, the pattern design is restricted because of bottom-contact-type defects. Thermal sintering of the printed patterns also leads to a longer processing time. To address these problems, we have developed several complementary processes. In this presentation, wet-on-wet, electrode-embedding, and push-pull processes and a newly developed high-resolution planographic method called adhesion contrast planography are discussed.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134517037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Development of a Ag/glass die attach adhesive for high power and high use temperature applications","authors":"Maciej Patelka, N. Sakai, Cathy Trumble","doi":"10.1109/ICEP.2016.7486838","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486838","url":null,"abstract":"The increasing power densities of certain semiconductor devices such as SiC and GaN require higher continuous use temperatures and high thermal properties. For example, one application is for a continuous use temperature of 300°C with SiC devices, with a die attach process at about 370°C. This paper describes development of an Ag/glass die attach paste which demonstrates high performance and reliability, for high temperature continuous use. The Ag/glass paste contains a unique crystallizing glass having a crystalline re-melt temperature of greater than 300°C and less than about 370°C. During the die attach process with Ag/glass paste, the crystallized glass component melts at about 350°C and wets the die and substrate surfaces. During the cool down of the die attach process, the glass crystallizes creating a robust structure having a re-melt temperature greater than 300°C. Therefore, die adhesion remains high for a 300°C continuous use temperature. Another key requirement of a die attach adhesive for use with SiC devices is power dissipation; i.e., heat dissipation. High thermal conductivity and very low interfacial thermal resistance for die attach parts have been demonstrated in this paper. Thermal resistance measurements (laser flash method) were consistently as low as 0.01Kcm2/W, while the bulk thermal conductivity was about 100W/mK. An inherent advantage of glass as the adhesive agent is its wettability on oxide or metal surfaces. This allows the option to use bare dies and substrates in lieu of metalized surfaces in certain applications, leading to the potential for significant cost savings. This new technology replaces the higher cost solder alloys and provides a high reliability option that meets the requirements for SiC device packaging.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134495875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Satou, Makoto Katsurayama, Akito Hiro, Hirokazu Sakakibara, K. Okamoto, Koichi Hasegawa
{"title":"Ultra thick photo resist for FO-WLP","authors":"K. Satou, Makoto Katsurayama, Akito Hiro, Hirokazu Sakakibara, K. Okamoto, Koichi Hasegawa","doi":"10.1109/ICEP.2016.7486890","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486890","url":null,"abstract":"With the current tremendous market growth of mobile devices toward the new era of Internet of Things/Internet of Everything, the requirements for semiconductor packaging structures are getting more challenging. In this situation, FO-WLP (Fan-Out Wafer Level Packaging) has been widely discussed as one of the major solutions in the 3D packaging area. We have been developing negative tone resists (ELPAC THB series) for re-distribution layer (RDL), solder bumps, copper pillars, and micro bumps, which show good lithographic properties, good chemical resistance for various plating chemicals, and good strippability. Based upon these technologies, we are now strongly focusing on new resists for finer RDL and high copper pillars in order to support FO-WLP players to efficiently fabricate their innovative packages. In this paper, we report on the latest ultra-thick photo resist to fabricate high copper pillars over 100um for FO-WLP. The new resist shows excellent coating performance to achieve 100um thickness in a single coat, or over 200um thickness with double coating, on 12 inch wafer. The resist provides good coating uniformity and TTV without bubbles, defects, wrinkles or other errors. On top of that, the new material design enables finer resolution for ultra-thick films, with an aspect ratio of 4 and beyond. We also report high copper pillars fabricated with the new THB resist. It is expected that the new ultra-thick resist will be the best candidate for FO-WLP. We will discuss the new material concept in more detail.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116994496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Evaluation of relationship between residual stress of ICs and package warpage caused by flip-chip bonding","authors":"T. Enami, O. Horiuchi, Younggun Han, H. Tomokage","doi":"10.1109/ICEP.2016.7486871","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486871","url":null,"abstract":"Relationship between the stress of ICs and package warpage caused by flip-chip bonding is evaluated using piezoresistor chip and is measured by Moiré measurement method. The die size is 9×9 mm2 with 200μm and 550μm in thickness. After non-conductive film laminating, the TEG chip is connected to the organic substrate or the Si interposer by FC bonding. The stress inside the chip was obtained in process of FC bonding by measuring the change in piezo-resistance. The warpage measured by moiré analysis method is in good agreement with the measured residual stress.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121125968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Electrochemical corrosion of interconnect materials by residual reductants","authors":"Ming-yan Lai, Jenn-Ming Song, Jing-Yuan Lin","doi":"10.1109/ICEP.2016.7486831","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486831","url":null,"abstract":"Reductants are widely used in up-to-date interconnect fabrication processes. Given that electrochemical corrosion of the interconnections may occur in humid circumstances under current stressing, this study explores the electrochemical properties of common interconnect materials, Cu and Ag, in the aqueous solutions of formic acid, glycol or ascorbic acid with various concentrations. Experimental results show that there exists no passivation stage on the polarization curves of Cu and Ag in those reductive solutions. Chronoamperometric study indicates that ascorbic acid corrodes Ag faster than the other reductants, while formic acid is most corrosive for Cu.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127287414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Sakamoto, S. Takanezawa, S. Tsuchikawa, M. Takekoshi, K. Oohashi, K. Morita
{"title":"Challenge to zero CTE and small cure shrinkage organic substrate core material for thin CSP package","authors":"N. Sakamoto, S. Takanezawa, S. Tsuchikawa, M. Takekoshi, K. Oohashi, K. Morita","doi":"10.1109/ICEP.2016.7486778","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486778","url":null,"abstract":"To reduce warpage of thinner package application such as POP (package on package), the ultra-low CTE (coefficient of thermal expansion) core materials has been developed. The resin system was originally designed by the concept of the combination of the hard and the soft segments. The hard segments composed of a stack structure of aromatic rings and the strong intermolecular force between them, which are the origin of the ultra-low CTE. The soft segments can follow the thermal motion of the glass fabric well due to the low elastic modulus. The CTE of the newly developed core material was as low as 0.7 ppm/°C. Then, it showed the ability to reduce warpage of PoP before/after assembly process. Our fundamental study revealed that the amount of the warpage is affected by not only the CTE but also the shrinkage of resin component in the core.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125903791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ching-Kuan Lee, Jen-Chun Wang, Yu-Min Lin, C. Zhan, Wen-Wei Shen, H. Fu, Yuan-Chang Lee, C. Chiang, Su-Ching Chung, Su-Mei Chen, Chia-Wen Fan, Hsiang-Hung Chang, W. Lo, Yung Jean Lu
{"title":"Reliability test for integrated Glass interposer","authors":"Ching-Kuan Lee, Jen-Chun Wang, Yu-Min Lin, C. Zhan, Wen-Wei Shen, H. Fu, Yuan-Chang Lee, C. Chiang, Su-Ching Chung, Su-Mei Chen, Chia-Wen Fan, Hsiang-Hung Chang, W. Lo, Yung Jean Lu","doi":"10.1109/ICEP.2016.7486780","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486780","url":null,"abstract":"In this paper, we investigated the reliability test for Glass interposer. The test vehicle is assembled glass interposer with chip, BT substrate, and PCB. The structure of a glass interposer with two RDL on the front-side and one RDL on the backside had been evaluated and developed. Key technologies, including via fabrication, topside RDL formation, micro-bumping, temporary bonding, silicon and glass thinning and backside RDL formation, were developed and integrated to perform well. The BT substrate design and PCB for electrical characterization of reliability tests are included as well. The results indicate that the device with the glass interposer can be integrated and there is also data showing the feasibility of the glass interposer for electronics applications.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116238429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}