{"title":"集成电路残余应力与倒装键合引起的封装翘曲关系的评估","authors":"T. Enami, O. Horiuchi, Younggun Han, H. Tomokage","doi":"10.1109/ICEP.2016.7486871","DOIUrl":null,"url":null,"abstract":"Relationship between the stress of ICs and package warpage caused by flip-chip bonding is evaluated using piezoresistor chip and is measured by Moiré measurement method. The die size is 9×9 mm2 with 200μm and 550μm in thickness. After non-conductive film laminating, the TEG chip is connected to the organic substrate or the Si interposer by FC bonding. The stress inside the chip was obtained in process of FC bonding by measuring the change in piezo-resistance. The warpage measured by moiré analysis method is in good agreement with the measured residual stress.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Evaluation of relationship between residual stress of ICs and package warpage caused by flip-chip bonding\",\"authors\":\"T. Enami, O. Horiuchi, Younggun Han, H. Tomokage\",\"doi\":\"10.1109/ICEP.2016.7486871\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Relationship between the stress of ICs and package warpage caused by flip-chip bonding is evaluated using piezoresistor chip and is measured by Moiré measurement method. The die size is 9×9 mm2 with 200μm and 550μm in thickness. After non-conductive film laminating, the TEG chip is connected to the organic substrate or the Si interposer by FC bonding. The stress inside the chip was obtained in process of FC bonding by measuring the change in piezo-resistance. The warpage measured by moiré analysis method is in good agreement with the measured residual stress.\",\"PeriodicalId\":343912,\"journal\":{\"name\":\"2016 International Conference on Electronics Packaging (ICEP)\",\"volume\":\"51 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-04-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 International Conference on Electronics Packaging (ICEP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICEP.2016.7486871\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference on Electronics Packaging (ICEP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICEP.2016.7486871","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Evaluation of relationship between residual stress of ICs and package warpage caused by flip-chip bonding
Relationship between the stress of ICs and package warpage caused by flip-chip bonding is evaluated using piezoresistor chip and is measured by Moiré measurement method. The die size is 9×9 mm2 with 200μm and 550μm in thickness. After non-conductive film laminating, the TEG chip is connected to the organic substrate or the Si interposer by FC bonding. The stress inside the chip was obtained in process of FC bonding by measuring the change in piezo-resistance. The warpage measured by moiré analysis method is in good agreement with the measured residual stress.
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