Evaluation of relationship between residual stress of ICs and package warpage caused by flip-chip bonding

Abstract

Relationship between the stress of ICs and package warpage caused by flip-chip bonding is evaluated using piezoresistor chip and is measured by Moiré measurement method. The die size is 9×9 mm2 with 200μm and 550μm in thickness. After non-conductive film laminating, the TEG chip is connected to the organic substrate or the Si interposer by FC bonding. The stress inside the chip was obtained in process of FC bonding by measuring the change in piezo-resistance. The warpage measured by moiré analysis method is in good agreement with the measured residual stress.