2016 International Conference on Electronics Packaging (ICEP)最新文献_第9页

Negative group delay characteristics of embedded transmission line with half-wavelength type F-SIR structure 半波长型F-SIR结构嵌入式传输线的负群延迟特性

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486773

Y. Kayano, H. Inoue

引用次数: 0

Reliable 4 million micro bumps at 7.6-um pitch interconnection technology for 3D stacked 16 million pixel image sensor 可靠的400万个7.6微米间距微凸点互连技术，用于3D堆叠1600万像素图像传感器

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486821

Y. Takemoto, N. Takazawa, M. Tsukimura, H. Saito, T. Kondo, H. Kato, J. Aoki, Kenji Kobayashi, S. Suzuki, Y. Gomi, S. Matsuda, Y. Tadaki

{"title":"Reliable 4 million micro bumps at 7.6-um pitch interconnection technology for 3D stacked 16 million pixel image sensor","authors":"Y. Takemoto, N. Takazawa, M. Tsukimura, H. Saito, T. Kondo, H. Kato, J. Aoki, Kenji Kobayashi, S. Suzuki, Y. Gomi, S. Matsuda, Y. Tadaki","doi":"10.1109/ICEP.2016.7486821","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486821","url":null,"abstract":"Our 3D stacked CMOS image sensor (CIS) has an ideal global shutter function with 16 million pixels and 4 million micro-bump interconnections placed at a 7.6-εm pitch between two silicon substrates, achieving interconnections with very low resistance. We confirmed the reliability of our 3D stacked interconnection technology by conducting reliability tests, which included heat cycle tests and high temperature and high humidity tests. The interconnections in our image sensor are comprised of 4 million micro bumps per chip. No increase in the number of failed interconnections or in micro-bump interconnection resistance was observed. For the heat cycle tests, our CIS is designed to have two test modes to detect failed interconnections by scanning all 4 million micro-bump interconnections in a short period. In the high temperature and high humidity tests, we tested the reliability of the interconnections by using test element group (TEG) chips to monitor the resistance precisely. We evaluated the effects of wafer bonding and the micro bumps on a MOS transistor with the TEGs, comparing two types of structures, one with micro bumps and one without, located under an nMOS transistor, and no difference in Vth among them was observed. These results prove that our 3D technology is reliable enough to be applied to our products.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127086845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Recent trends of package warpage and measurement metrologies 包装翘曲和测量计量的最新趋势

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486789

W. K. Loh, R. Kulterman, H. Fu, M. Tsuriya

{"title":"Recent trends of package warpage and measurement metrologies","authors":"W. K. Loh, R. Kulterman, H. Fu, M. Tsuriya","doi":"10.1109/ICEP.2016.7486789","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486789","url":null,"abstract":"Current consumer products are designed based on an “outside in” process where parameters such as consumer experience and portability are prioritized to define the system and component design and performance targets. This drives innovation in electronic packaging to challenge the existing design boundaries and norms. One of the challenges faced by the electronic industry is managing the package warpage characteristics for seamless component to board assembly process. As part of a continuous effort, iNEMI has collaborated with individual companies to establish a sampling of current trends of electronic packaging warpage, and also initiated an effort to evaluate state-of-the-art dynamic warpage measurement metrologies. The former objective has provided a new batch of donated parts for warpage characterization which included Package on Package (PoP) memory, System in Package (SiP), Fine pitch Ball Grid Array (FBGA) as well as Flip Chip BGA (FCBGA) with and without a lid (heat spreader). The dynamic warpage metrologies considered were based on thermal shadow moiré, 3D digital image correlation (3D DIC), fringe projection moiré and confocal technique. In this paper, the majority of the work covered will be the dynamic warpage characteristics of donated components and a brief description of metrologies under consideration.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128211948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Reliability design on wearable device for initial osteoarthritis (OA) on knee joints 膝关节初发性骨关节炎可穿戴设备的可靠性设计

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486801

H. Hsu, Pin-Chieh Wang, Jia-Jung Wang, S. Fu

{"title":"Reliability design on wearable device for initial osteoarthritis (OA) on knee joints","authors":"H. Hsu, Pin-Chieh Wang, Jia-Jung Wang, S. Fu","doi":"10.1109/ICEP.2016.7486801","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486801","url":null,"abstract":"More than 750,000 females and 500,000 males in Taiwan will be diagnosed as osteoarthritis (OA) patient in 2018. Also, two thirds of orthopedics outpatients are found to be associated with OA. Therefore, it becomes necessary and essential to detect the severity of OA knee joints as early as possible and to release/reduce the knee pain induced by OA. In recent years, the wearable technology has become the fastest growing electronic technology because of size miniaturization, low power consumption, intelligence, and convenience features. There are two features of wearables, i.e. the space is limited and the substrate used should be flexible and stretchable. In this paper, an innovated wireless wearable apparatus has been developed to detect OA symptom. A chip embedded flexible PDMS substrate with ultrafine conduct lines and laser-drilled vias is required for this innovated wearable devices. The packaging technology developed in this work is to vertically/horizontally assemble ultra-thin heterogeneous ICs, sensors, passive components, interposer or flexible substrate into a single package. In addition, reliability test and evaluation are conducted to evaluate one-time maximum bending test and duration bending test. In this paper, “develop a packaging technique for smart wireless wearable devices for OA detection” and “develop test standards for smart wireless wearable apparatus” will be presented.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125625557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Partial discharges in ceramic substrates - correlation of electric field strength simulations with phase resolved partial discharge measurements 陶瓷衬底中的局部放电——电场强度模拟与相分辨局部放电测量的相关性

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486884

C. F. Bayer, U. Waltrich, Amal Soueidan, E. Baer, A. Schletz

{"title":"Partial discharges in ceramic substrates - correlation of electric field strength simulations with phase resolved partial discharge measurements","authors":"C. F. Bayer, U. Waltrich, Amal Soueidan, E. Baer, A. Schletz","doi":"10.1109/ICEP.2016.7486884","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486884","url":null,"abstract":"High voltages and the edges of the metallization on ceramic substrates (AMB, DBA, DBC, HTCC, LTCC) lead to high electric field strengths. In the vicinity of the metal edges these high electric field strengths induce partial discharges in the ceramic insulation and in the covering synthetics and thereby represent one key degradation mechanism of power modules. In this work the correlation of the simulated electric field strength with phase resolved partial discharge (PRPD) measurements has been investigated. For the simulation of the electric field strength a new method was used to bypass numerical artifacts. The simulated values showed that it is possible to reduce the electric field strength by an adaption of the metallization structure. There the distance of the upper and the lower metallization to the rim of the ceramic was changed relative to each other. Due to this variation a reduction of the electric field strength by about 30 % can be reached by choosing the optimum distance compared to state of the art modules. In PRPD measurements for ceramic substrates (AlN/Al2O3 by DCB) we examined whether the field reduction leads to higher partial discharge inception voltages (PDIV). The measurements were executed on layouts with different dimensions of the upper and lower metallization relative to each other as well as for 3 different thicknesses of the ceramic insulation (1 mm and 0.63 mm AlN DBC, 0.63 mm and 0.38 mm Al2O3 DBC) layer. An increase from 20 % to 35 % of the PDIV was measured for layouts which were designed according to the findings from the simulation with respect to field strength reduction. Finally, the calculated electric field strength and the measured PDIV were correlated.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131628800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Thermal resistance evaluation by high-temperature transient thermal analysis method for SiC power modules 基于高温瞬态热分析方法的SiC功率模块热阻评估

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486814

F. Kato, H. Nakagawa, H. Yamaguchi, Hiroshi Sato

{"title":"Thermal resistance evaluation by high-temperature transient thermal analysis method for SiC power modules","authors":"F. Kato, H. Nakagawa, H. Yamaguchi, Hiroshi Sato","doi":"10.1109/ICEP.2016.7486814","DOIUrl":"https://doi.org/10.1109/ICEP.2016.7486814","url":null,"abstract":"Thermal resistance evaluation of silicon carbide (SiC) power module for high-temperature operation has been performed in order to define the precise thermal resistance in real package structure. Transient thermal analysis method using SiC-Schottky barrier diode (SBD) is applied to measure the thermal structure function in wide temperature range from 50°C to 250°C. The module structure consists of a SBD, a silicon nitride-active metal brazed copper (SiN-AMC) and Cu baseplate which are bonded each other by Gold Germanium (AuGe) solder. We found that it is difficult to define the thermal resistance components of the SiN-AMC and baseplate in the thermal structure function. The reference module structure without SiN-AMC is prepared for isolation of thermal resistances. The thermal resistance of SiN-AMC is successfully defined by comparing the structure functions without and with SiN-AMC. This phenomenon is attributed to thermal spreading effect in the high thermal conductivity material (Cu baseplate) based on present experiment. The thermal resistance in the module structure are successfully defined into 4 components. Furthermore, temperature dependency of the thermal resistances is also measured even in the middle of the package structure in wide temperature range from 50°C to 250°C.","PeriodicalId":343912,"journal":{"name":"2016 International Conference on Electronics Packaging (ICEP)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-04-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132630432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Room-temperature wafer bonding using smooth gold thin films for wafer-level MEMS packaging 使用光滑金薄膜的室温晶圆键合用于晶圆级MEMS封装

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486864

Y. Kunimune, K. Okumura, E. Higurashi, T. Suga, K. Hagiwara

引用次数: 1

Epoxy molding compound for fingerprint sensor 指纹传感器用环氧成型化合物

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486888

J. Tabei, H. Sasajima, Takeshi Mori

引用次数: 7

System Power Integrity and radiation analysis of packaging by CMOS inverter CMOS逆变器封装系统功率完整性及辐射分析

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486909

Pei-Chen Kuo, Yu-Yung Wu, S. Wu

引用次数: 0

Application dependency of 3-D integrated hybrid solid-state drive system with through-silicon via technology 采用硅通孔技术的三维集成混合固态驱动系统的应用依赖性

2016 International Conference on Electronics Packaging (ICEP) Pub Date : 2016-04-20 DOI: 10.1109/ICEP.2016.7486787

Y. Sugiyama, Tomoaki Yamada, C. Matsui, Takahiro Onagi, K. Takeuchi

引用次数: 1