Warpage characterization analysis for Embedded package technology

Abstract

The Embedded die in substrate (EDS) market has grown significantly over the past several years and it is now one of the fastest growing packaging technologies in the semiconductor industry driven by smaller form factor, better heat dissipating, low noise emission, higher levels of integration and better performance. In addition, for power management and mobile-wireless application the embedded technology had been evaluated to replace assembles fabrication not only thinner thickness but superior electrical performance. However, Embedded Die causes severe package warpage issue due to CTE mismatch happened on diffusion bond process. In this work, the three Dimensional Warpage Metrology Analyzer (3D-WMA), as a non-contact optical deformation measurement method used to measure unit package warpage behavior with different temperatures. Reducing the warpage issue of package, the parametric factors on the structure and material would be investigated. These design guides are then studied by finite element modeling to understand mechanism for warpage improvement and the dielectric material property selection is critically factoring for warpage control. The measured warpage data agrees very well with the predicted one that the maximum discrepancy is within 3%. Based on the above justification, it starts to carry out the parametric study. Initially, changed prepreg can improve the warpage 64%. Besides, Cu layer should be thick and soldermask layer should be thin. Furthermore, asymmetric structure design of Cu layer and soldermask layer is another effective for warpage reduction. Impact from structural design and material property selection is studied in this paper.