{"title":"Simulation of thermal oxidation and diffusion processes by parallel PDE solver L/sub i/SS","authors":"W. Joppich, S. Mijalkovic","doi":"10.1109/SISPAD.1996.865286","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865286","url":null,"abstract":"In this paper a rigorous approach to simulate thermal oxidation and diffusion phenomena is presented. Because the numerical problems will increase in future, especially when looking towards three-dimensional process simulation, special emphasis is laid upon a parallel approach which additionally uses an optimal order solution method. Based on an environment for the parallel solution of elliptic and parabolic PDEs, L/sub i/SS, such a tool was developed.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122635296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Accurate chip scale topography modeling in O(n) run time","authors":"K. Lucas, X. Li, M. Noell, C. Yuan, A. Strojwas","doi":"10.1109/SISPAD.1996.865320","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865320","url":null,"abstract":"Currently, semiconductor manufacturing topography models for design and process optimization can investigate only a tiny portion of a die at a given time. Therefore, important coupling effects between areas are ignored. As interconnect capacitance and resistance become the limiting factor to chip speed, the coupling effects of process variations upon timing delays will become critical. Additionally, current process models are unable to consider known die scale effects such as stepper lens aberrations, tilt, scaling, polishing variations and etch loading effects. We are introducing a model for accurately simulating die scale effects upon semiconductor topography in O(n) run time, where n is the number of mask features, and with efficient memory usage. The inherently parallel model combines existing process models with new developments. The model provides a better interface between design and process areas for complete die performance optimization studies.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"83 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132658476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Lades, A. Schenk, U. Krumbein, G. Wachutka, W. Fichtner
{"title":"Temperature-dependent study of 6H-SiC pin-diode reverse characteristics","authors":"M. Lades, A. Schenk, U. Krumbein, G. Wachutka, W. Fichtner","doi":"10.1109/SISPAD.1996.865271","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865271","url":null,"abstract":"Silicon carbide is a promising material for special semiconductor applications, such as high-power and high-temperature devices. To date, much effort has been devoted to improving the process and device technology. With the progress in this field, the need for accurate modeling of device characteristics arises. This implies the formulation of proper physical models and their validation. We report on investigations of the reverse characteristics of a 6H-SiC pin diode using the multi-dimensional device simulator DESSIS/sub -ISE/ discussing the contributions of different physical mechanisms to the blocking behavior and their temperature dependence in the range of 300-623 K.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117257582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sang-Hoon Lee, Kyung-Ho Kim, Jin-Kyu Park, Chang-hoon Choi, J. Kong, Won-Woo Lee, Wong-Seong Lee, Jei-Hwan Yoo, Sooin Cho
{"title":"A realistic methodology for the worst case analysis of VLSI circuit performances","authors":"Sang-Hoon Lee, Kyung-Ho Kim, Jin-Kyu Park, Chang-hoon Choi, J. Kong, Won-Woo Lee, Wong-Seong Lee, Jei-Hwan Yoo, Sooin Cho","doi":"10.1109/SISPAD.1996.865318","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865318","url":null,"abstract":"Summary form only given. Minimising the circuit layout feature size can lead to improved performance, but it may also reduce the manufacturing yield. The smaller dimensions increase the relative variability of the process and make the circuit sensitive to process fluctuations such as, photo mask, depo/etch and furnace. In order to produce circuit designs that are more robust, it is crucial for designers to verify that circuit performances meet specifications across the entire range of process fluctuations. The driving force of previous work has thus been to come up with a simple and effective worst case design. In this work, a new approach to the statistical worst case of full-chip circuits, using the Principal Component Analysis (PCA) and the Gradient Analysis (GA), is proposed and verified. This method enables designers not only to predict the standard deviations of circuit performance but also to track circuit performances associated with process shift by measuring e-tests. Experimental qualification of the method is described using a 0.25 /spl mu/m 256 Mbit DRAM.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116069594","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"TED model including the dissolution of extended defects","authors":"S. Kamohara, A. Shimizu, S. Yamamoto, K. Kubota","doi":"10.1109/SISPAD.1996.865284","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865284","url":null,"abstract":"The requirement for the formation of the shallow junction has arisen as device dimensions shrink into the submicron regime. The shallow junctions are generally formed by low-energy ion implantation followed by low thermal-budget processing. However, simulations of dopant diffusion during the thermal processing have not been very successful, mainly due to the transient enhanced diffusion (TED). TED continues until the concentrations of the point defects, interstitial silicon, and vacancies become almost their thermal equilibrium values. For accurate simulation of TED, the effect of the extended defect dissolution cannot be neglected. In this work, we propose a new TED model which includes the extended defect dissolution.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122021349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"The application of TCAD in industry","authors":"J. Mar","doi":"10.1109/SISPAD.1996.865313","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865313","url":null,"abstract":"The key to making use of TCAD in industry is matching available capabilities to specific applications to multiply information from available experimental wafers. The art of using such partial capabilities is the focus of this paper. The following sections will describe applications of TCAD in four areas: technology selection, process optimization, process control, and design optimization.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122076537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Full-band Monte Carlo simulation of high-energy transport and impact ionization of electrons and holes in Ge, Si, and GaAs","authors":"M. Fischetti, N. Sano, S. Laux, K. Natori","doi":"10.1109/SISPAD.1996.865265","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865265","url":null,"abstract":"In this work we have computed the rate for impact ionization ab initio and have employed this rate in full-band Monte Carlo simulations in order to determine the high-energy carrier-phonon deformation potentials. We have considered transport and impact ionization of electrons and holes in Ge, Si, and GaAs, the valence bands being treated with nonlocal empirical pseudopotentials and spin-orbit interaction. The impact ionization rates have been computed using three different approximations: (1) the ab initio rate, which accounts for energy and momentum conservation and for the dependence of the Coulomb matrix element on both initial and final states, (2) the constant-matrix-element (CME) approximation, which employee a constant Coulomb matrix element, and (3) the random-k approximation, which relaxes momentum-conservation.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127825943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Soft error rate modeling and analysis of SOI/TFT SRAM's","authors":"P. Oldiges","doi":"10.1109/SISPAD.1996.865297","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865297","url":null,"abstract":"Addresses methods to increase the maximum allowable gain including lifetime reduction, decreasing SOI film thickness and increasing the channel doping. The effect of lowered power supply voltages on the gain of the parasitic device and ramifications of that for the SER of SOI SRAMs is also discussed.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132127661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"BARAS: Novel and highly efficient simulation system for process control sweeping and statistical variation","authors":"T. Tatsumi, K. Ansai, K. Hayakawa, M. Mukai","doi":"10.1109/SISPAD.1996.865315","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865315","url":null,"abstract":"For the realization of today's miniaturization and low voltage drive of ULSIs, it has become much more important to understand and predict the effect of process variations on device performance. Predicting the quantitative effect of every process variation on device characteristics has the following advantages: in designing, required performance range can be appropriately specified, and in manufacturing, when some device characteristic is out of specification, processes to control can be feed-forwarded for proper production. In order to realize this by utilizing simulations, it would be crucial for the simulation system to have a user interface with ease of operation and an efficient data processing ability based on the actual process parameter distribution of the manufacturing equipment. There are some simulation tools which enable the above tasks. However, they have difficulty in handling mask shape variations and in utilizing actual process distributions which do not follow the Gaussian distribution. We have developed BABAS, the automatic simulation system capable of very efficient process control sweeping, statistical variation analysis and output data processing, which has functions for producing input data files automatically and has an easy-to-use GUI. Furthermore, BABAS has succeeded in reducing CPU time drastically by utilizing moment expansion method and enabled Monte Carlo simulations based on real process parameter variations.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122377698","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A new approach to fully unstructured three-dimensional Delaunay mesh generation with improved element quality","authors":"P. Fleischmann, S. Selberherr","doi":"10.1109/SISPAD.1996.865308","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865308","url":null,"abstract":"Mesh generation is known to play a critical role in semiconductor device and process simulation. We present a new approach suitable for dealing with the increasing complexity of the device boundaries and interfaces as well as moving boundaries. It is recently understood that techniques which have worked well in the past (octree methods, intersection and bisection based methods, cartesian methods) are at their limits today. It is in this spirit that we developed a fully unstructured gridding method which we believe is the only potential way to deal with the complexity of future devices and to handle moving boundary situations. Our algorithm also incorporates local improvement of element quality by non-delaunay quality measures, while still maintaining the Delaunay property.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124082767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}