SOI/TFT SRAM软错误率建模与分析

1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095) Pub Date : 1996-09-02 DOI:10.1109/SISPAD.1996.865297

P. Oldiges

{"title":"SOI/TFT SRAM软错误率建模与分析","authors":"P. Oldiges","doi":"10.1109/SISPAD.1996.865297","DOIUrl":null,"url":null,"abstract":"Addresses methods to increase the maximum allowable gain including lifetime reduction, decreasing SOI film thickness and increasing the channel doping. The effect of lowered power supply voltages on the gain of the parasitic device and ramifications of that for the SER of SOI SRAMs is also discussed.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Soft error rate modeling and analysis of SOI/TFT SRAM's\",\"authors\":\"P. Oldiges\",\"doi\":\"10.1109/SISPAD.1996.865297\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Addresses methods to increase the maximum allowable gain including lifetime reduction, decreasing SOI film thickness and increasing the channel doping. The effect of lowered power supply voltages on the gain of the parasitic device and ramifications of that for the SER of SOI SRAMs is also discussed.\",\"PeriodicalId\":341161,\"journal\":{\"name\":\"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-09-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SISPAD.1996.865297\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.1996.865297","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

提出了增加最大允许增益的方法，包括减少寿命、减少SOI薄膜厚度和增加通道掺杂。本文还讨论了电源电压降低对寄生器件增益的影响以及对SOI sram的SER的影响。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Soft error rate modeling and analysis of SOI/TFT SRAM's

Addresses methods to increase the maximum allowable gain including lifetime reduction, decreasing SOI film thickness and increasing the channel doping. The effect of lowered power supply voltages on the gain of the parasitic device and ramifications of that for the SER of SOI SRAMs is also discussed.

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来源期刊

1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)

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