{"title":"Accuracy and convergence properties of a one-dimensional numerical non-quasi-static MOSFETs model for circuit simulation","authors":"E. Robilliart, E. Dubois","doi":"10.1109/SISPAD.1996.865328","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865328","url":null,"abstract":"Accurate modeling of static currents, conductance and charge dynamics are essential for the design of digital and specially for analog circuits. In the analog domain, the shortcomings of many modeling approaches often originate from transistors biased between linear and saturation regimes where discontinuities limit the accuracy and the convergence properties. Moreover, the finite charging/discharging time of the channel may significantly degrade the performances of modern circuit architectures due to charge injection. However, most MOSFET models reveal poor prediction capabilities for high frequency operations for which quasi-static (QS) operation is often violated. In this paper we discuss the accuracy and numerical properties of a one-dimensional CAD-oriented model. It is shown that the proposed model is continuous over all operating regimes and suitable for the analysis of long and short channel MOSFETs. The most interesting feature of our model, an implicit non-quasi-static (NQS) treatment of the charge redistribution, is outlined. Finally, convergence properties are discussed with a special emphasis on the mobility model and on the related nonlinear resolution scheme.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124265079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Robust simulation for the hysteresis phenomena of SOI MOSFET's by quasi-transient method","authors":"R. Ikeno, K. Asada","doi":"10.1109/SISPAD.1996.865296","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865296","url":null,"abstract":"Device simulation of SOI MOSFET's has several difficulties originating from the floating body features. One of them is numerical instability of the solution of carrier densities in channel region due to the floating body effect, which is unlike the conventional MOSFET's. Another problem is physical possibility of multiple solutions even at the same bias condition, which results in the hysteresis characteristics such as Single-Transistor Latch (STL) phenomena. To improve robustness of SOI simulation, we have developed a Quasi-Transient (QT) method for static (DC) mode analysis, and showed that fast and stable DC analysis is realized in device simulation of SOI MOSFET's. In this paper, we show that the STL phenomena of SOI MOSFET's are successfully simulated with the QT method for analysing floating body and parasitic bipolar effects of thin-film SOI devices.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125128508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Cellular automata for device simulation-concepts and applications","authors":"G. Zandler, M. Saraniti, A. Rein, P. Vogl","doi":"10.1109/SISPAD.1996.865263","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865263","url":null,"abstract":"We present a discussion of various concepts of cellular automata for semiconductor transport in the context of device simulation. A newly developed transformation for the kinetic terms of the Boltzmann equation into deterministic transition rules are found to be superior to probabilistic rules, allowing a complete suppression of statistical errors without any loss in numerical performance. To take advantage of the high speed of the resulting Cellular Automaton, a fast and flexible multigrid-solver for the Poisson equation has been developed. This enables us to study also fluctuations of transport quantities, which determine the high frequency noise behavior of MOSFETs, within the Cellular Automata approach. The reliability of the new CA approach for nanostructured devices is demonstrated by a study of gate length influence onto the drain current characteristics of a novel vertically grown MOSFET.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123403683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Hyodo, S. Taji, N. Yoshida, M. Kameda, H. Watanabe, I. Shiota
{"title":"Analysis of boron pile-up at the Si-SiO/sub 2/ interface using 2-D process and device simulation","authors":"T. Hyodo, S. Taji, N. Yoshida, M. Kameda, H. Watanabe, I. Shiota","doi":"10.1109/SISPAD.1996.865285","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865285","url":null,"abstract":"An accurate channel doping profile calculated by a process simulator is essential to the prediction of MOSFET threshold voltage (Vth). However it can not be easily calibrated to measurements, since SIMS which is believed to be the most accurate profiling technique at present, has /spl plusmn/10% error on the depth scale, /spl plusmn/15% on the concentration scale. Moreover measured concentrations in the near-surface region are not reliable. In this study the correction method for SIMS profile is presented. Also by using well-calibrated channel doping profiles, the boron pile-up layer situated on the Si side of the Si-SiO/sub 2/ interface is analyzed.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122024213","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Elasto-viscoplastic modeling for three-dimensional oxidation process simulation","authors":"J. Lee, M. Son, C. S. Yun, K. Kim, H. Hwang","doi":"10.1109/SISPAD.1996.865283","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865283","url":null,"abstract":"With continued minimization of the device structure and the development of new semiconductor process, the characteristics of submicron transistors in ULSI or GSI technologies are strongly affected by multi-dimensional device structure. Process simulations have contributed to a better understanding of device physics and to the development of new processing techniques. Device isolation has been most commonly achieved through the use of LOCOS (LOCal Oxidation of Silicon) or LOCOS derivatives due to its process simplicity and excellent isolation characteristics. With device sizes shrinking, three-dimensional oxidation process simulations are required to predict the accurate shape of the oxide, the stress distribution and the three-dimensional effects, such as center effect and mask lifting effect. Therefore more accurate and robust oxidation model is needed in order to ensure optimal control of the technological oxidation process. In this paper, we developed the three-dimensional process simulator of oxidation with a newly proposed elastoviscoplastic model. In this model, the oxidant diffusion is solved by BEM (Boundary Element Method) which is suitable for moving boundary condition and surface mesh.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117090881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Three-dimensional photoresist exposure and development simulation","authors":"H. Kirchauer, Siegfried Selberherr","doi":"10.1109/SISPAD.1996.865291","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865291","url":null,"abstract":"Among all technologies photolithography holds the leading position in pattern transfer in today's semiconductor industry. The reduction of the lithographic feature sizes towards or even beyond the used wavelength and the increasing nonplanarity of devices create complicated problems for the lithography process. A three-dimensional photolithography simulator including mask illumination, resist exposure and resist development is a cost effective tool for further improvements. We present a complete three-dimensional simulation model focusing on the resist exposure and resist development step.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130011733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modeling and characterization of three-dimensional effects in physical etching and deposition simulation","authors":"Z. Hsiau, E. Kan, D. Bang, J. Mcvittie, R. Dutton","doi":"10.1109/SISPAD.1996.865279","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865279","url":null,"abstract":"With the ever decreasing transistor feature sizes, scaling of interconnect has caused many new challenges in fabrication technology. Three-dimensional (3D) geometrical effects due to mechanical stress and electrical charge on short-length or sharp-corner conductors and dielectrics has become more prominent in analyses of IC process variation, leakage current and reliability. In this paper modeling and characterization of 3D effects for etching and deposition, extended from physical models calibrated in 2D, will be discussed in view of boundary movement accuracy and robustness, and methodology for calibration with direct measurements. An L-shaped test structure will be used as a technology example.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133038595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Importance of inter-valley phonon scattering on mobility enhancement in strained Si MOSFETs","authors":"S. Takagi, J. Hoyt, J. Welser, J. Gibbons","doi":"10.1109/SISPAD.1996.865247","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865247","url":null,"abstract":"It has recently been reported that strained Si MOSFETs fabricated with relaxed SiGe layer exhibit very high mobility at room temperature, almost twice as high as that in conventional Si MOSFETs. While strained Si MOSFETs, compatible with Si LSI technology, are promising as the devices for the high speed, room temperature applications, the understanding of the carrier transport in strained Si is still lacking. In order to clarify the mechanism of the mobility enhancement, calculations of the subband structure and phonon-limited mobility in the inversion layer of strained Si were performed for the first time, compared with the calculations for the inversion layer of unstrained (conventional) Si. The effect of the band splitting due to strain was successfully incorporated in the subband calculation. It is demonstrated that the suppression of inter-valley phonon scattering is essential to the mobility enhancement in strained Si MOSFETs.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115804604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Two-dimensional calibration of dopant transport models for submicron CMOS transistors","authors":"F. Lau, P. Kupper, K. Gebhardt","doi":"10.1109/SISPAD.1996.865299","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865299","url":null,"abstract":"In most cases complex process models for damage enhanced diffusion (DED) are calibrated from one-dimensional measurements (vertical SIMS or spreading resistance). MOS transistors in the submicron regime however are inherently two-dimensional devices. In this paper we analyse, whether a one-dimensional calibration of an advanced DED model is sufficient for a correct lateral subdiffusion of the source/drain dopants.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121990631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Syo, Y. Akiyama, S. Kumashiro, I. Yokota, S. Asada
{"title":"A triangular mesh with the interface protection layer suitable for the diffusion simulation","authors":"T. Syo, Y. Akiyama, S. Kumashiro, I. Yokota, S. Asada","doi":"10.1109/SISPAD.1996.865325","DOIUrl":"https://doi.org/10.1109/SISPAD.1996.865325","url":null,"abstract":"An automatic Delaunay partitioned mesh generation which is effective in reduction of numerical errors in a diffusion process near the interface or in the thin layer is proposed. An interface protection layer which consists of a rectangular mesh locally conformed to a material interface is introduced. A validity of the interface protection layer for avoiding an artificial threshold voltage shift of about 1 V due to a boron penetration through a pMOS gate oxide is demonstrated.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128806037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}