T. Syo, Y. Akiyama, S. Kumashiro, I. Yokota, S. Asada
{"title":"A triangular mesh with the interface protection layer suitable for the diffusion simulation","authors":"T. Syo, Y. Akiyama, S. Kumashiro, I. Yokota, S. Asada","doi":"10.1109/SISPAD.1996.865325","DOIUrl":null,"url":null,"abstract":"An automatic Delaunay partitioned mesh generation which is effective in reduction of numerical errors in a diffusion process near the interface or in the thin layer is proposed. An interface protection layer which consists of a rectangular mesh locally conformed to a material interface is introduced. A validity of the interface protection layer for avoiding an artificial threshold voltage shift of about 1 V due to a boron penetration through a pMOS gate oxide is demonstrated.","PeriodicalId":341161,"journal":{"name":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-09-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1996 International Conference on Simulation of Semiconductor Processes and Devices. SISPAD '96 (IEEE Cat. No.96TH8095)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SISPAD.1996.865325","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
An automatic Delaunay partitioned mesh generation which is effective in reduction of numerical errors in a diffusion process near the interface or in the thin layer is proposed. An interface protection layer which consists of a rectangular mesh locally conformed to a material interface is introduced. A validity of the interface protection layer for avoiding an artificial threshold voltage shift of about 1 V due to a boron penetration through a pMOS gate oxide is demonstrated.