Analysis of boron pile-up at the Si-SiO/sub 2/ interface using 2-D process and device simulation

Abstract

An accurate channel doping profile calculated by a process simulator is essential to the prediction of MOSFET threshold voltage (Vth). However it can not be easily calibrated to measurements, since SIMS which is believed to be the most accurate profiling technique at present, has /spl plusmn/10% error on the depth scale, /spl plusmn/15% on the concentration scale. Moreover measured concentrations in the near-surface region are not reliable. In this study the correction method for SIMS profile is presented. Also by using well-calibrated channel doping profiles, the boron pile-up layer situated on the Si side of the Si-SiO/sub 2/ interface is analyzed.