A realistic methodology for the worst case analysis of VLSI circuit performances

Abstract

Summary form only given. Minimising the circuit layout feature size can lead to improved performance, but it may also reduce the manufacturing yield. The smaller dimensions increase the relative variability of the process and make the circuit sensitive to process fluctuations such as, photo mask, depo/etch and furnace. In order to produce circuit designs that are more robust, it is crucial for designers to verify that circuit performances meet specifications across the entire range of process fluctuations. The driving force of previous work has thus been to come up with a simple and effective worst case design. In this work, a new approach to the statistical worst case of full-chip circuits, using the Principal Component Analysis (PCA) and the Gradient Analysis (GA), is proposed and verified. This method enables designers not only to predict the standard deviations of circuit performance but also to track circuit performances associated with process shift by measuring e-tests. Experimental qualification of the method is described using a 0.25 /spl mu/m 256 Mbit DRAM.