Sixth international symposium on quality electronic design (isqed'05)最新文献_第9页

Functional verification of networked embedded systems 网络化嵌入式系统的功能验证

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.59

N. Bombieri, F. Fummi, G. Pravadelli

引用次数: 4

P/G pad placement optimization: problem formulation for best IR drop P/G垫位优化:最佳IR下降的问题配方

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.89

A. Dubey

{"title":"P/G pad placement optimization: problem formulation for best IR drop","authors":"A. Dubey","doi":"10.1109/ISQED.2005.89","DOIUrl":"https://doi.org/10.1109/ISQED.2005.89","url":null,"abstract":"IR drop minimization has become very difficult for non-flip chip packaged designs due to technology shrink and increasing design frequencies. Different constituents of IR drop on a wire-bond chip (where pads are placed at the die-periphery) are \"package-ball to bond-pad drop\", \"bond-pad to internal global power ring drop\" and \"internal local power ring drop\". Optimization equations are developed to minimize IR drop from the lead-finger-frame to the standard cell power rails on the die by placing the P/G pads optimally for a given power network. Further, optimization equations are developed to minimize trace wire length on package for P/G pads drawing highest current. The cost functions in the optimization equations target minimum IR drop for those regions of the chip that are switching at maximum speed. By use of our cost function for optimizing P/G pad placement, results on the representative chip with about 15 million gates and several hard macros show an improvement of 10% to 15% in worst IR drop value for different floorplans (one floorplan with uniform power density, and the other floorplan with maximum power density much higher than the average power density of the design).","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131005086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Deep submicron CMOS integrated circuit reliability simulation with SPICE 深亚微米CMOS集成电路可靠性仿真

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.37

Xiaojun Li, Bing Huang, J. Qin, X. Zhang, M. Talmor, Z. Gur, J. Bernstein

{"title":"Deep submicron CMOS integrated circuit reliability simulation with SPICE","authors":"Xiaojun Li, Bing Huang, J. Qin, X. Zhang, M. Talmor, Z. Gur, J. Bernstein","doi":"10.1109/ISQED.2005.37","DOIUrl":"https://doi.org/10.1109/ISQED.2005.37","url":null,"abstract":"The purpose of the paper is to introduce a new failure rate-based methodology for reliability simulation of deep submicron CMOS integrated circuits. Firstly, two of the state-of-the-art MOSFET degradation models are reviewed. They have been developed into reliability simulation tools and commercialized in industry for many years, however, their inherent limitations of characterizing circuit lifetime, including tedious processes for extracting device degradation parameters and model fitting parameters, impeded their wide applications in the product's front-end design process. Secondly, a set of accelerated lifetime models for the most important intrinsic silicon degradation mechanisms are proposed. These lifetime models correlate a device's electrical operating parameters to its mean time to failure (MTTF) in simple forms. Finally, a new failure rate-based SPICE reliability simulation methodology is developed, in which MTTF and failure in time (FIT) are the primary reliability parameters to be characterized. The power of this new reliability simulation method, due to its simplicity, makes it an important design-for-reliability tool for electronic product developers.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125907814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Noise library characterization for large capacity static noise analysis tools 噪声库表征大容量静态噪声分析工具

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.85

A. Gyure, Alireza Kasnavi, S. Lo, P. Tehrani, William Shu, M. Shahram, Joddy W. Wang, Jindrich Zejda

引用次数: 4

Design of high performance sense amplifier using independent gate control in sub-50nm double-gate MOSFET 采用独立栅极控制的亚50nm双栅极MOSFET的高性能感测放大器设计

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.44

S. Mukhopadhyay, H. Mahmoodi, K. Roy

引用次数: 29

TFT-LCD application specific low power SRAM using charge-recycling technique 使用电荷回收技术的TFT-LCD应用特定的低功耗SRAM

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.121

Keejong Kim, C. Kim, K. Roy

{"title":"TFT-LCD application specific low power SRAM using charge-recycling technique","authors":"Keejong Kim, C. Kim, K. Roy","doi":"10.1109/ISQED.2005.121","DOIUrl":"https://doi.org/10.1109/ISQED.2005.121","url":null,"abstract":"We propose a novel low power charge-recycling SRAM (CR-SRAM) for portable TFT-LCD applications. In portable TFT-LCD applications, low power considerations are becoming more important for longer battery lifetime. To reduce the power consumption in SRAMs, the source-line, connected to the source terminals of the driver MOSFETs, is controlled, so that it is zero in the active mode and has a positive bias voltage in the stand-by mode. However, the overhead power consumed during the control of source-line voltage is considerable due to the large capacitive load on the source-line. Applying a charge-recycling technique to the source-line allows reduction of the power dissipation of the source-biased SRAM. Moreover, by exploiting the sequential access pattern of the TFT-LCD memory, the proposed CR-SRAM can efficiently reduce the power dissipation of the control circuit for charge recycling. The proposed CR-SRAM is implemented in a 0.18 /spl mu/m technology and shows 68% and 14% power reduction compared to conventional SRAM (CON-SRAM) and source-biased SRAM (SB-SRAM), respectively. We also evaluate the power consumptions under various temperatures and row driver clock frequencies. Experimental results show that the percentage of power savings due to charge recycling increases with the higher frequency and achieved a maximum of 25% at 250 MHz.","PeriodicalId":333840,"journal":{"name":"Sixth international symposium on quality electronic design (isqed'05)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121511901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Issues and challenges in ramp to production 投产过程中的问题和挑战

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.72

Arun Shrimali, Anand Venkitachalam, Ravi Arora

引用次数: 0

Analysis and design of LVTSCR-based EOS/ESD protection circuits for burn-in environment 基于lvtscr的EOS/ESD老化保护电路的分析与设计

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.17

O. Semenov, H. Sarbishaei, M. Sachdev

引用次数: 6

Design of sub-90 nm circuits and design methodologies 90纳米以下电路的设计与设计方法

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.45

A. Devgan, R. Puri, Sachin Sapatnaker, T. Karnik, R. Joshi

引用次数: 0

Dynamic test compaction for bridging faults 桥接故障动态测试压实

Sixth international symposium on quality electronic design (isqed'05) Pub Date : 2005-03-21 DOI: 10.1109/ISQED.2005.48

I. Pomeranz, S. Reddy

引用次数: 0