Analysis and design of LVTSCR-based EOS/ESD protection circuits for burn-in environment

Abstract

As technology feature size is reduced, ESD becomes one of the dominant failure modes due to the lower gate oxide breakdown voltage. Also, the holding voltage of LVTSCR devices is reduced with operating temperature increase. As a result, during stress testing (burn-in), the risk of latch-up in LVTSCR is extremely high. In this paper, a new latch-up free LVTSCR-based protection circuit is proposed. It can be reliably used in sub-0.18 /spl mu/m CMOS technologies and burn-in environment. The proposed ESD circuit has higher holding voltage by 1.5/spl times/ than the conventional LVTSCR structure at burn-in temperature. Under 3 kV HBM ESD stress, the developed LVTSCR-based protection circuit has the voltage peak less than the conventional LVTSCR structure and GG-MOSFET by 2/spl times/ and 1.25/spl times/, respectively.